3D Memory Device Vertical Pillar Self-Aligned Transistors
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Solution Overview
Problem
In the field of Integrated Circuits, specifically 3D memory devices, the performance and functionality are hindered by degrading wire performance due to scaling, which affects the efficiency and power consumption, and existing 3D stacking techniques face challenges in reducing wire lengths and development costs while maintaining high yield and simplicity.
Innovation Solution
The development of 3D memory devices with self-aligned horizontally-oriented memory transistors, where vertical pillars act as sources or drains, and the use of tungsten control gates, along with recrystallized channel regions, to enhance transistor performance and reduce wire lengths through innovative layer transfer and integration techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If 3D stacking of semiconductor devices is implemented, then wire lengths are reduced and wiring delay is kept low, but wire performance degrades due to scaling
Solution Approach 1:
The patent transitions from planar 2D integration to three-dimensional 3D stacking of memory layers. By stacking memory layers vertically and connecting them through vertical interconnects, the horizontal wire lengths are significantly reduced while maintaining functional connectivity. This dimensional change allows multiple memory layers to share common word lines and bit lines, reducing the overall interconnect length and improving signal integrity.
2Volume of moving object
If multiple layers of transistors are constructed separately and bonded with through-silicon vias, then 3D stacking is achieved, but manufacturing complexity and development costs increase
Solution Approach 1:
The patent merges multiple separate memory layer constructions into a single integrated structure. Instead of fabricating individual layers separately and bonding them with complex through-silicon via processes, the invention uses a unified monolithic 3D approach where multiple memory layers are formed in an integrated manner, sharing common interconnect structures and reducing the overall manufacturing complexity.
Solution Approach 2:
The patent implements universal interconnect structures that serve multiple functions across different memory layers. Common word lines and bit lines are shared across multiple memory layers, and the same lithography and fabrication processes are used for all layers, eliminating the need for separate processing steps for each layer and reducing development costs.
3Length of moving object
If monolithic 3D technology is used, then wire lengths are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication processes where the monolithic 3D structure automatically maintains precise alignment during manufacturing. The self-aligned formation of contact holes, interconnect structures, and transistor gates eliminates the need for complex alignment procedures and reduces sensitivity to lithographic variations, thereby maintaining high manufacturing precision even as wire lengths are reduced in the 3D stacked architecture.
Data Source
AI summary
A 3D memory device, the device including: a first vertical pillar, the first vertical pillar includes a transistor source; a second vertical pillar, the second vertical pillar includes the transistor drain, where the first vertical pillar and the second vertical pillar each functions as a source or functions as a drain for a plurality of overlaying horizontally-oriented memory transistors, where at least of one of the plurality of overlaying horizontally-oriented memory transistors is disposed between the first vertical pillar and the second vertical pillar, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following a same lithography step, and where the first vertical pillar includes metal.