3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration density due to the high cost and complexity of fine pattern forming technologies, necessitating the development of three-dimensional semiconductor memory devices with improved reliability and higher integration density.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a peripheral logic structure on a semiconductor substrate, featuring a horizontal semiconductor layer with multiple doped layers and vertically stacked electrodes, along with vertical structures connected to the horizontal layer, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked above each other, with word lines, bit lines, and select lines extending vertically through the stack. This dimensional change enables significantly higher integration density while maintaining compatibility with existing semiconductor manufacturing processes.
2Quantity of substance
If fine pattern forming technology is advanced to increase integration, then integration density improves, but process equipment cost increases
Solution Approach 1:
Instead of increasing pattern fineness in the planar direction, the patent stacks multiple memory cell layers vertically. This approach achieves higher integration density by utilizing the vertical dimension rather than pushing the limits of fine pattern forming technology, thereby avoiding the need for extremely expensive advanced lithography equipment.
Solution Approach 2:
The patent implements a stacked memory structure where multiple memory cell layers are nested vertically above each other. Each layer contains memory cells formed by the intersection of word lines, bit lines, and select lines. This nesting arrangement achieves high integration density using standard manufacturing processes without requiring extreme pattern fineness.
3Speed
If dopant concentration is increased to reduce sheet resistance, then erase operation speed improves, but dopant diffusion increases causing junction leakage
Solution Approach 1:
The patent employs selective doping with different impurity concentrations in different regions of the memory cell structure. The first doped region (contact region) has a first impurity concentration optimized for low sheet resistance and fast erase operation, while the second doped region (channel region) has a second impurity concentration that prevents excessive dopant diffusion and junction leakage. This local quality differentiation resolves the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the dopant concentration parameter across different regions and depths of the memory cell structure. By implementing a graded doping profile with varying impurity concentrations in different layers and regions, the patent optimizes both erase operation speed (through low sheet resistance in contact regions) and junction reliability (through controlled doping in channel regions to prevent leakage).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a highly reliable and high-density three-dimensional semiconductor memory device, reducing sheet resistance and suppressing dopant diffusion to improve erase operation speed and reduce junction leakage, thereby overcoming the limitations of two-dimensional devices.
Implementation Method 1
a first semiconductor layer provided on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities
Implementation Method 2
a first semiconductor layer provided on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration
Data Source
AI summary
Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.