3D Semiconductor Memory Vertical Stacking Integration Density
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration due to the high cost and complexity of processing equipment required for fine pattern formation, which restricts their ability to increase memory cell density and integration.
Innovation Solution
The development of three-dimensional semiconductor memory devices with vertically stacked gate electrodes, source structures, and dummy vertical semiconductor patterns that are electrically insulated from the source conductive patterns, allowing for enhanced integration and reliability by avoiding the need for expensive processing equipment and preventing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern formation to increase integration, then integration density is improved, but processing equipment cost and complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking, where multiple gate electrodes are stacked vertically over the same substrate area. This dimensional change allows multiple memory cells to occupy the same footprint space, dramatically increasing integration density without requiring finer lateral patterning, thus avoiding the need for expensive fine-patterning equipment
2Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern formation to increase integration, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
By stacking gate electrodes vertically in the third dimension, the patent achieves higher integration density using standard lithography processes without requiring advanced fine-patterning equipment. This approach maintains manufacturing simplicity and reduces equipment costs while still increasing the number of memory cells per chip
3Ease of manufacture
If dummy vertical semiconductor patterns are electrically connected to source conductive patterns, then manufacturing is simplified, but leakage currents occur
Solution Approach 1:
The patent applies different electrical properties to different dummy vertical semiconductor patterns based on their location. Patterns in the first region are electrically connected to source conductive patterns for manufacturing simplicity, while patterns in the second region are electrically insulated to prevent leakage currents. This localized differentiation of electrical properties resolves the contradiction between manufacturing simplicity and reliability
Data Source
AI summary
A three-dimensional semiconductor memory device may include a substrate comprising a cell array region and a connection region, an electrode structure including a plurality of gate electrodes sequentially stacked on a surface of the substrate and extending from the cell array region to the connection region, a first source conductive pattern between the electrode structure and the substrate on the cell array region, and a cell vertical semiconductor pattern and a first dummy vertical semiconductor pattern that penetrate the electrode structure and the first source conductive pattern and extend into the substrate. The cell vertical semiconductor pattern may contact the first source conductive pattern. The first dummy vertical semiconductor pattern may be electrically insulated from the first source conductive pattern.