3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the need for expensive equipment to form fine patterns, leading to a demand for three-dimensional semiconductor memory devices that can enhance reliability and integration density.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a horizontal semiconductor layer with vertically stacked cell gate electrodes and ground selection gate electrodes, interconnected through structures connecting the gate electrodes to a peripheral logic structure, improving integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation techniques to increase integration density, then integration density is improved, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple cell strings are stacked in the vertical direction, allowing multiple memory cells to occupy the same footprint area. This dimensional change dramatically increases integration density without requiring proportionally more expensive fine pattern formation equipment, as the stacking can be achieved through sequential deposition and formation processes rather than requiring ultra-fine lateral patterning.
2Reliability
If three-dimensional semiconductor memory devices are designed with complex electrode interconnections to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory device into multiple independent cell strings, each with its own selection transistors and memory cells. These cell strings are stacked vertically but can be controlled independently through the through-interconnection structures. This segmentation allows fault isolation and improves reliability while the modular nature of the segmented design actually reduces overall system complexity compared to a monolithic structure.
Solution Approach 2:
The through-interconnection structures serve as intermediary elements that connect the control electrodes of different cell strings vertically. These intermediaries simplify the control architecture by providing direct vertical pathways for control signals, reducing the need for complex lateral routing and intermediate control logic, thereby improving reliability while managing device complexity.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.