3D Memory Cell Layout With Vertical Transistors and Simpler Interconnects
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach limits, with planar transistors occupying more area and complicating interconnect structures, leading to reduced memory cell efficiency and increased leakage current.
Innovation Solution
The implementation of vertical transistors, such as multi-gate or single-gate transistors, which reduce transistor area, simplify interconnect layouts, and decrease coupling capacitance by arranging bit lines and storage units on opposite sides of the transistors, allowing for more efficient memory cell arrays and improved fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors are used in memory cells, then the transistors can be easily manufactured with conventional processes, but the transistors occupy more area and increase interconnect complexity
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to vertical (3D) transistor architecture. The vertical transistor structure extends the channel in the vertical direction rather than laterally, fundamentally changing the dimensional approach to reduce footprint and simplify interconnect routing while maintaining manufacturability through adapted fabrication processes
2Area of moving object
If planar transistors are scaled to smaller sizes, then memory cell area is reduced, but fabrication complexity and cost increase significantly
Solution Approach 1:
Instead of continuing to scale planar transistors laterally to reduce area, the patent adopts vertical transistors that extend the channel vertically. This dimensional change allows memory cell area reduction without proportionally increasing fabrication complexity, as the vertical structure can be formed using modified conventional processes rather than requiring increasingly complex planar scaling techniques
3Device complexity
If planar transistors are used, then the interconnect structure becomes more complex, but vertical transistors require new fabrication approaches
Solution Approach 1:
The vertical transistor architecture simplifies interconnect structure by reducing the number of interconnect layers needed compared to planar designs. The fabrication process challenge is addressed by developing vertical transistor formation techniques that build upon conventional semiconductor manufacturing, using vertical epitaxial growth and selective etching rather than entirely new approaches
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.