3D Memory Cell Vertical Transistor Layout for Lower Leakage
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach limits, and existing transistors complicate the arrangement of interconnect structures, leading to reduced memory cell array efficiency and increased leakage current.
Innovation Solution
The use of vertical transistors, such as multi-gate or single-gate transistors, replaces planar transistors in memory cells, allowing for reduced transistor area, simplified interconnect layouts, and increased bit line process margin, with the memory cell array and peripheral circuits formed on different wafers and bonded face-to-face, reducing chip size and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If planar transistors are used in memory cells, then the interconnect structures can be arranged, but the transistor area increases and leakage current increases
Solution Approach 1:
The patent transitions from planar (2D) transistors to vertical (3D) transistors, changing the dimensional orientation of the transistor structure. This vertical configuration reduces the footprint area while maintaining electrical functionality, directly addressing the contradiction between transistor area and leakage current by enabling more compact cell designs with reduced parasitic effects
2Device complexity
If planar transistors are used, then the memory cell structure is simple, but the interconnect layout becomes complex and memory cell array efficiency decreases
Solution Approach 1:
By adopting vertical transistors, the patent enables more efficient interconnect routing in the planar direction. The vertical channel orientation frees up lateral space for optimized bit line and word line arrangements, improving memory cell array efficiency while maintaining manageable structural complexity through standardized vertical transistor fabrication processes
3Ease of manufacture
If memory cell array and peripheral circuits are on the same wafer, then fabrication is simpler, but chip size increases and electrical connection distance increases
Solution Approach 1:
The patent divides the memory device into separate functional modules: memory cell arrays fabricated on one wafer and peripheral circuits on another wafer. These segmented modules are then bonded together through wafer-level bonding, enabling short-distance electrical interconnections while maintaining fabrication simplicity through modular, standardized processing steps for each separate module
Solution Approach 2:
The patent introduces wafer-level bonding as an intermediary process that connects separately fabricated memory cell arrays and peripheral circuits. This bonding interface serves as a mediator that enables compact integration with short electrical connection paths while allowing each module to be optimized independently during fabrication
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.