3D Semiconductor Memory Device Vertical Via Wiring Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional semiconductor memory devices face limitations in increasing integration density due to the need for a large number of metal layers, which increases manufacturing complexity and cost, while also potentially degrading operation characteristics.
Innovation Solution
The semiconductor memory device design includes a cell region with vertical channels and interlayer dielectric layers, a step region with contacts, and a peripheral region with under and top wiring lines, utilizing vertical vias to reduce the number of metal layers required by distributing wiring lines across multiple layers effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stack number of row lines is increased to increase integration density, then the degree of integration is improved, but the number of wiring lines coupled to row lines increases proportionally, requiring more metal layers which increases device complexity
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional structure by stacking multiple interlayer dielectric layers and electrode layers vertically. This allows wiring lines to be distributed across multiple stacked layers rather than requiring an increased number of metal layers in a single plane, thereby increasing integration density without proportionally increasing the number of metal layers.
Solution Approach 2:
The patent implements a nested structure where multiple interlayer dielectric layers and electrode layers are stacked within each other vertically. The first interlayer dielectric layer contains first wiring lines, while the second interlayer dielectric layer contains second wiring lines, creating a nested arrangement that efficiently utilizes vertical space to reduce the overall number of metal layers required.
2Quantity of substance
If more metal layers are used to accommodate increased wiring lines, then the number of wiring lines can be increased, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the wiring structure into multiple distinct interlayer dielectric layers, each containing specific wiring lines. The first interlayer dielectric layer contains first wiring lines coupled to first row lines, while the second interlayer dielectric layer contains second wiring lines coupled to second row lines. This segmentation allows for organized, modular manufacturing processes that reduce complexity compared to creating a single dense layer of wiring lines.
Solution Approach 2:
By distributing wiring lines across multiple vertically stacked interlayer dielectric layers rather than concentrating them in fewer metal layers, the patent reduces the total number of metal layers required. This vertical distribution simplifies the manufacturing process by reducing the number of sequential metal deposition and patterning steps needed.
3Device complexity
If the number of metal layers is reduced to simplify manufacturing, then device complexity is reduced, but the ability to accommodate sufficient wiring lines for high integration is compromised
Solution Approach 1:
The patent achieves high integration density with fewer metal layers by utilizing the vertical dimension through stacked interlayer dielectric layers. Each dielectric layer contains wiring lines that are vertically separated, allowing multiple wiring functions to be accomplished within a reduced number of horizontal metal layers, thus maintaining integration density while reducing overall device complexity.
Solution Approach 2:
The interlayer dielectric layers serve multiple functions: they provide electrical insulation between different wiring levels, mechanically support the wiring structures, and enable the vertical stacking architecture. This multi-functionality allows the structure to accommodate sufficient wiring lines for high integration without requiring an equivalent increase in the number of dedicated metal layers.
Data Source
AI summary
A semiconductor memory device includes a cell region defined with vertical channels which pass through electrode layers and interlayer dielectric layers alternately stacked; a step region disposed adjacent to the cell region in a first direction, and defined with contacts coupled to the electrode layers extending in different lengths; a first opening passing through the electrode layers and the interlayer dielectric layers in the step region; a second opening passing through the electrode layers and the interlayer dielectric layers in the cell region; under wiring lines coupled with a peripheral circuit defined on a substrate; top wiring lines disposed over the electrode layers and the interlayer dielectric layers, and coupled with the contacts; and vertical vias coupling the under and top wiring lines, wherein the vertical vias include first vertical vias which pass through the first opening and second vertical vias which pass through the second opening.