3D Memory Row-Line Layout With Vertical Vias to Cut RC Delay
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Solution Overview
Problem
The increasing number of row lines in three-dimensional memory devices leads to a rise in wiring lines, which decreases the degree of integration and increases the size of the memory device, necessitating an efficient wiring line layout method to maintain capacity and performance.
Innovation Solution
A three-dimensional memory device is designed with row lines stacked alternately with interlayer dielectric layers and vias extending vertically to couple the row lines to a peripheral circuit, using a method that involves forming sacrificial layers, interlayer dielectric layers, and conductive patterns to create a staircase structure for efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of row lines is increased to increase the degree of integration, then the memory capacity is improved, but the number of wiring lines increases and the device size increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by forming vias that extend vertically from the substrate to couple with projections on the side surfaces of row lines. This vertical dimension allows multiple row lines to be stacked without proportionally increasing the horizontal device area, enabling higher integration density through vertical stacking of memory cells and wiring structures.
Solution Approach 2:
The patent implements nested wiring structures where vias are positioned within the vertical projection of row lines, and coupling lines are routed through intermediate layers to connect multiple row lines to a single peripheral circuit interface. This nesting allows multiple signaling paths to share common wiring resources, reducing the total number of external wiring lines required.
2Quantity of substance
If the number of row lines is increased to increase the degree of integration, then the memory capacity is improved, but the number of wiring lines increases
Solution Approach 1:
The patent designs coupling lines that can serve multiple functions: they electrically connect row lines to peripheral circuits, provide signal routing between different memory blocks, and enable shared use of peripheral circuit interfaces across multiple row lines. This multi-functionality reduces the total number of dedicated wiring lines required for each row line connection.
Solution Approach 2:
The patent introduces intermediate coupling lines and coupling structures that act as mediators between row lines and peripheral circuits. Instead of directly connecting each row line to peripheral circuit interfaces, the coupling lines serve as intermediary pathways that aggregate multiple row line connections, thereby reducing the number of direct wiring lines required.
3Reliability
If wiring lines are extended to connect row lines and peripheral circuits, then electrical coupling is achieved, but RC delay increases causing functional errors
Solution Approach 1:
The patent reduces wiring path length by utilizing vertical vias that directly connect to side surface projections of row lines, creating shorter electrical paths compared to traditional planar routing. The three-dimensional wiring architecture minimizes the horizontal distance signals must travel, thereby reducing RC delay while maintaining reliable electrical coupling.
Data Source
AI summary
A method for manufacturing a three-dimensional memory device, comprises: forming, on a substrate, a sacrificial layer including a plurality of sacrificial patterns for vias and a sacrificial pattern for a row line; forming an interlayer dielectric layer that covers the sacrificial pattern for a row line and the sacrificial pattern for a via coupled to the sacrificial pattern for a row line and that has a plurality of holes exposing sacrificial patterns for vias, from among the plurality of sacrificial patterns for vias, that are not coupled to the sacrificial pattern for a row line; forming a plurality of first conductive patterns in the plurality of holes; repeating the forming of the sacrificial layer; and replacing the plurality of sacrificial layers with a conductive material.