3D Non-Volatile Memory Layout With Vertical Wiring Integration
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Solution Overview
Problem
The challenge is to reduce the size of non-volatile memory devices while maintaining high integration density, which is hindered by the increasing complexity of operating circuits and wiring structures as memory cells are miniaturized.
Innovation Solution
A non-volatile memory device is designed with a substrate, a first semiconductor layer containing a memory cell array, and a second semiconductor layer with a peripheral circuit. A protrusion structure with a wire extends into both semiconductor layers, allowing for a more compact design by reducing the area occupied by external signal pads and wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced for high integration density, then storage capacity increases, but operating circuit complexity and wiring structure complexity increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical wiring structures. Bit lines and word lines are extended in the vertical direction (first direction) through the substrate, allowing memory cells to be accessed from the top surface without requiring complex lateral wiring. This dimensional change reduces wiring complexity while enabling high-density memory cell arrays.
Solution Approach 2:
The memory device is divided into multiple semiconductor layers (first semiconductor layer with memory cell array, second semiconductor layer with peripheral circuits) stacked vertically. This segmentation allows different functional blocks to be separated into distinct layers, reducing the complexity of interconnections within each layer while maintaining high integration density through vertical stacking.
2Quantity of substance
If memory cell size is reduced for high integration density, then storage capacity increases, but semiconductor chip area reduction faces technical limits
Solution Approach 1:
The invention utilizes the vertical dimension (first direction perpendicular to substrate) for wiring and signal transmission. Bit lines and word lines extend vertically through the substrate rather than laterally across the chip surface. This allows memory cells to be densely packed in the horizontal plane without requiring proportionally increasing wiring area, effectively decoupling storage capacity from chip area.
Solution Approach 2:
Multiple functional layers are nested vertically: the substrate contains vertically extending bit lines and word lines, the first semiconductor layer contains the memory cell array, and the second semiconductor layer contains peripheral circuits. This nested vertical arrangement maximizes the use of three-dimensional space, allowing high storage capacity within a limited chip footprint.
3Area of stationary object
If external signal pads and wires area is reduced for compact design, then device size decreases, but manufacturing complexity increases
Solution Approach 1:
Signal transmission paths are moved from the chip periphery (lateral wiring) to the vertical dimension. Bit lines and word lines extend vertically through the substrate to contact pads on the top surface, eliminating the need for extensive lateral wiring and large peripheral signal pads. This reduces the overall device footprint while the vertical wiring structure can be integrated into the standard memory cell fabrication process.
Solution Approach 2:
The wiring structures (bit lines, word lines) are merged with the memory cell stack structure. The same vertical columns that form the memory cells also serve as the signal transmission paths, eliminating separate wiring layers and reducing manufacturing steps. This integration simplifies the overall fabrication process while achieving compact device dimensions.
Data Source
AI summary
A non-volatile memory device includes a substrate, a first semiconductor layer including a memory cell array on the substrate, a second semiconductor layer including a peripheral circuit that is configured to write data to or read the data from the memory cell array, where the second semiconductor layer is on the first semiconductor layer, and a protrusion structure including a wire that extends into at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer, where the protrusion structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and where the protrusion structure extends in a second direction that is perpendicular to the first direction.