3D Memory Circuit Layout With Shared Via and Digitline Formation
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently integrating vertically-stacked memory cells with conductive vias, leading to increased circuit size and reduced density.
Innovation Solution
The formation of vertically-alternating insulative and memory-cell tiers with horizontal transistors, where access lines are horizontally extended into a connection region, allowing for simultaneous fabrication of digitlines and conductive-via constructions, reducing the connection region size and enhancing circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are integrated with conductive vias using existing technologies, then memory functionality is achieved, but connection region size increases and circuit density decreases
Solution Approach 1:
The patent merges the formation of digitlines and conductive-via constructions into a single simultaneous fabrication process. By combining these two separate fabrication operations into one, the connection region can serve dual purposes: housing both digitline connections and conductive via structures. This merging eliminates the need for separate dedicated spaces for each function, thereby reducing overall connection region size while maintaining high circuit density.
Solution Approach 2:
The connection region is designed to perform multiple functions simultaneously. It serves as both the connection point for digitlines and the location for conductive-via constructions that access memory-cell tiers. This multi-functional design allows the same physical space to fulfill multiple electrical connection requirements, reducing the total area needed for connections while increasing the effective utilization of the connection region.
2Ease of manufacture
If access lines are extended horizontally into connection region, then simultaneous fabrication of digitlines and conductive vias is enabled, but manufacturing process complexity increases
Solution Approach 1:
The access lines are extended horizontally into the connection region during the memory array formation stage, before the final connection region patterning occurs. This preliminary extension of access lines establishes the geometric framework early in the fabrication process, allowing subsequent digitline and conductive via formations to proceed simultaneously without requiring additional alignment steps or complex sequencing. The preliminary action simplifies the overall manufacturing complexity by pre-positioning critical features.
Data Source
AI summary
A method used in forming memory circuitry comprising memory cells comprises forming vertically-alternating insulative tiers and memory-cell tiers. The memory cells individually comprise a horizontal transistor comprising a gate that comprises part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier. The access lines extend horizontally from the memory-array region into a connection region. Over a same time period and using the same processing steps, digitlines are formed in the memory-array region that individually directly electrically couple to the horizontal transistors in different ones of the memory-cell tiers and conductive-via constructions are formed in the connection region that individually directly electrically couple to individual of the access lines. Other embodiments, including structure, are disclosed.