3D Memory Via Extension Regions for Contact Alignment
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, the challenge of increasing memory density is addressed by transitioning to three-dimensional (3D) memory architectures, but manufacturing complexity and cost rise, and misalignment issues in lithography processes lead to decreased contact surface and increased contact resistance, potentially causing electrical disconnections and low device yield.
Innovation Solution
The method involves forming contact pads in via extension regions of 3D memory structures using a dual damascene process, which includes forming hard masks, etching via extension regions, and filling metal material to create contact wires and pads, providing an enlarged alignment window and reducing misalignment risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes using improved process technology, then memory density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. This dimensional change allows memory density to increase vertically rather than requiring continued lateral scaling, thereby reducing manufacturing complexity and cost associated with sub-lithographic feature sizes while maintaining high memory density
2Quantity of substance
If feature sizes of memory cells are reduced to approach upper limit density, then memory density increases, but planar process techniques become challenging and costly
Solution Approach 1:
By adopting 3D memory architecture with vertical stacking of memory cells, the patent achieves high memory density without requiring further reduction of lateral feature sizes. This avoids the manufacturing challenges and increased costs associated with pushing planar feature sizes to their physical limits
3Manufacturing precision
If lithography processes are used to form contact structures in 3D memory, then alignment is required, but misalignment issues lead to decreased contact surface and increased contact resistance
Solution Approach 1:
The patent forms via extension regions that protrude from the sides of target vias before contact structures are formed. This preliminary structural preparation creates an enlarged alignment window, allowing contact structures to be formed with greater tolerance to misalignment, thereby maintaining adequate contact surface area and reducing contact resistance even when perfect alignment is not achieved
Solution Approach 2:
The patent modifies the geometric parameters of the via structure by adding via extension regions. This changes the contact formation parameters, creating a larger effective contact area and more relaxed alignment requirements, which improves both manufacturing precision tolerance and electrical connection reliability
Data Source
AI summary
Embodiments of 3D memory structures and methods for forming the same are disclosed. A method for forming a three-dimensional (3D) memory structure includes forming a dielectric layer on a substrate and forming a first plurality of openings in the dielectric layer at a staircase region of the 3D memory structure. The method also includes forming a second plurality of openings in the dielectric layer at a peripheral device region of the 3D memory structure and forming at least one hard mask layer in the first plurality of openings of the staircase region and in the second plurality of openings of the peripheral device region. The method further includes etching the dielectric layer using the at least one hard mask layer to form first and second pluralities of via extension regions in top portions of the respective first and second pluralities of openings. The method further includes disposing a first conductive material in the first and second pluralities of openings to form respective first and second pluralities of contact wires. The method also includes disposing a second conductive material in the first and second pluralities of via extension regions to form first and second pluralities of contact pads and forming first and second pluralities of lead wires on the first and second pluralities of contact pads, respectively.