3D Semiconductor Memory Stack Layout for Via Isolation
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost of fine pattern forming technology, hindering the increase in data storage capacity and performance while maintaining affordability.
Innovation Solution
A three-dimensional semiconductor memory device with a vertical channel structure is developed, featuring a stack of interlayer dielectric layers and gate electrodes, a mold structure with sacrificial layers, and a planarization insulating layer to enhance integration and electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and fine pattern forming costs
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory layers are stacked in the vertical direction, enabling significantly higher integration density without requiring finer lateral patterning. This dimensional change allows increased data storage capacity while avoiding the need for expensive fine pattern forming equipment.
2Productivity
If three-dimensional vertically stacked structures are implemented, then integration and data storage capacity increase, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers including first and second substrates, lower and upper insulating layers, mold structures, and stacked memory layers. Each layer can be independently fabricated and assembled, simplifying the overall manufacturing process despite the vertical complexity. This segmentation allows standard fabrication processes to be applied repeatedly to build the 3D structure.
Solution Approach 2:
Lower and upper insulating layers are introduced as intermediary elements between the stacked memory layers and substrates. These insulating layers provide electrical isolation and mechanical support, enabling the vertical stacking architecture to function reliably. The mold structures serve as intermediaries during fabrication to define and protect the vertical channel regions.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure with peripheral transistors on the first substrate, a second substrate on the peripheral circuit structure, a lower insulating layer in contact with a side surface of the second substrate, a top surface of the lower insulating layer having a concave profile, a first stack on the second substrate, the first stack including repeatedly alternating first interlayer dielectric layers and gate electrodes, and a first mold structure on the lower insulating layer, the first mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and a top surface of the first mold structure being at a level lower than a topmost surface of the first stack.