3D Memory Test Structures for Staircase Via Open Detection
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Solution Overview
Problem
In three-dimensional (3D) non-volatile memory devices, ensuring accurate electrical coupling of via structures to staircase interface portions is challenging due to varying heights, leading to potential open circuits and difficulties in identifying problematic connections.
Innovation Solution
The formation of test structures next to memory sub-arrays with staircase interface portions and via structures that emulate the memory sub-array profiles, allowing for electrical coupling in series to test and identify connection issues without interfering with normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via structures are used to electrically couple memory sub-arrays with staircase interface portions, then electrical connection is achieved, but identification of open circuit defects becomes difficult due to varying heights
Solution Approach 1:
The patent creates test structures that are copies of the actual memory sub-arrays, including identical via structures and staircase interface portions. These test structures replicate the electrical connection paths and height variations, allowing defects to be mirrored and identified without affecting normal memory operation. The test structures serve as surrogates for detecting open circuits in the actual memory array.
Solution Approach 2:
The test structures act as intermediary elements between the test signal and the actual memory sub-arrays. By introducing these intermediate test structures with identical via structures and staircase profiles, the system can indirectly detect connection defects that would be difficult to measure directly on the memory array itself.
2Difficulty of detecting and measuring
If test structures are formed next to memory sub-arrays, then defect identification capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory device into functional memory sub-arrays and separate test structures. This segmentation allows the test functions to be isolated from the operational memory, enabling independent testing without interfering with normal memory operations. The test structures are distinct segments that can be activated only during testing phases.
Solution Approach 2:
The test structures are formed during the same fabrication process as the memory sub-arrays, preparing the testing capability in advance. This preliminary action ensures that test structures are already in place and configured before the device is operational, allowing immediate defect identification without adding post-fabrication complexity.
3Difficulty of detecting and measuring
If serial electrical coupling of test structures is implemented, then connection issues can be isolated, but manufacturing precision requirements increase
Solution Approach 1:
The test structures are precise copies of the memory sub-arrays, replicating the via structures, staircase interface portions, and electrical connection paths. This copying approach ensures that the test structures have identical manufacturing characteristics and precision requirements, allowing defect isolation without introducing additional manufacturing variability.
Data Source
AI summary
A memory device includes a plurality of memory sub-arrays. Each of the memory sub-arrays is accessed through a staircase of word lines (WLs) and a plurality of interconnect structures. The memory device includes a plurality of test structures. Each of the test structures corresponds to one of the memory sub-arrays, and includes: (i) a staircase of test WLs that emulate the staircase of WLs coupled to the corresponding memory sub-array, and (ii) a plurality of test interconnect structures that emulate the interconnect structures coupled to the corresponding memory sub-array. The plurality of test structures are electrically coupled to one another in series.