3D Memory Backside Via Layout With Etch Stop Metal Plates
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Solution Overview
Problem
Current semiconductor technologies face challenges in forming efficient electrical connections for backside via structures in three-dimensional memory devices, particularly in providing reliable electrical pathways for backside contact pads and metal plates in complex memory arrays.
Innovation Solution
The method involves forming an alternating stack of insulating and sacrificial material layers, patterning to create stepped surfaces, and replacing sacrificial material layers with electrically conductive layers and metal plates, while forming connection via structures through dielectric material portions to establish contact with backside contact pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional connection methods are used for backside via structures, then fabrication processes become simpler, but electrical connection reliability deteriorates
Solution Approach 1:
Metal plates are formed at the backside substrate surface before the via structures are created. This preliminary placement of conductive plates provides a ready-made electrical pathway foundation, ensuring reliable connections are established before the complex via formation process begins, thereby improving connection reliability while managing fabrication complexity.
Solution Approach 2:
Metal plates serve as intermediary conductive elements between the backside contact pads and the frontside memory structures. These plates act as mediators that facilitate electrical connection through the substrate, improving connection reliability by providing a dedicated conductive pathway that bridges the gap between contact pads and memory cell structures.
2Reliability
If metal plates are formed at backside substrate surface, then electrical pathways are improved, but fabrication steps increase
Solution Approach 1:
The formation of metal plates is merged with the existing backside contact pad fabrication process. By combining these operations into a single integrated process flow, the patent improves electrical pathway reliability without proportionally increasing fabrication steps, as the metal plate formation is integrated into the contact pad creation sequence rather than being a separate additional step.
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of a source layer, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, a dielectric material portion laterally offset from the alternating stack, a connection via structure vertically extending through the dielectric material portion and contacting a front side surface of a metallic plate, and a backside contact pad in electrical contact with the metallic plate.