3D Memory Via Structure for Capacity and Connection Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and product reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a substrate structure with conductive plate layers, gate electrode layers, channel structures, and bonding metal layers, along with via structures and connecting structures, to enhance data storage capacity and reliability by optimizing the arrangement and connection of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional manner to increase data storage capacity, then the data storage capacity is improved, but the product reliability deteriorates due to increased complexity and potential failure points
Solution Approach 1:
The semiconductor device is divided into multiple substrate structures (first substrate structure and second substrate structure) that are bonded together. Each substrate structure contains separate circuit elements, gate electrode layers, and channel structures, allowing the memory to be segmented into functional modules that can be independently manufactured and tested before bonding, thereby maintaining reliability while achieving 3D stacking for increased capacity
Solution Approach 2:
The patent implements a stacked configuration where the second substrate structure is disposed on and connected to the first substrate structure. The via structures extend through the plate layer to connect gate electrode layers at different levels, creating a nested 3D architecture where multiple layers of memory cells are integrated vertically, increasing storage capacity without proportionally increasing failure risk through modular design
2Reliability
If via structures are designed with larger bottom face width for better connectivity, then the electrical connection reliability is improved, but the manufacturing precision requirements worsen due to tapered structure formation
Solution Approach 1:
The via structures are designed with a tapered configuration where the bottom face width is greater than the top face width. This parameter change in the via geometry allows for improved electrical connection reliability by providing a larger bonding area at the bottom face that contacts the plate layer, while the tapered shape can be achieved through controlled deposition or etching processes that manage the precision requirements of the manufacturing steps
3Quantity of substance
If gate electrode layers are stacked closely together to increase density, then the data storage capacity is improved, but the electrical isolation between layers worsens
Solution Approach 1:
The plate layer is configured with specific local properties including a conductive material composition and a controlled thickness range (50 nm to 200 nm) that provides electrical isolation between stacked gate electrode layers. This local quality control at the plate layer interface allows gate electrode layers to be stacked closely together for increased density while maintaining electrical isolation to prevent harmful interference between adjacent memory cell layers
Data Source
AI summary
A semiconductor device includes first and second substrates connected to each other. The second substrate includes a plate layer having first and second faces. Gate electrode layers are disposed on the first face of the plate layer. Channel structures extend through the gate electrode layers. Word-line cutting structures extend through the gate electrode layers and are spaced apart from each other. Via structures are disposed on the second face of the plate layer. Via connecting structures are disposed on the top face of the via structures. A width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures. A width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.