3D Memory Via Connections for Bit and Source Line Routing
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Solution Overview
Problem
Existing 3-dimensional semiconductor memory circuits require significant silicon real estate and conductor resources for signal routing between bit lines and circuitry, which are precious and desirable to minimize.
Innovation Solution
A process involving buried contacts, staircase structures, and conductor-filled trenches to create via connections that access bit and source lines from both above and beneath the 3-dimensional array, eliminating the need for additional silicon real estate and conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional signal routing methods are used in 3-dimensional memory circuits, then bit lines and source lines can be accessed, but significant silicon real estate and conductor resources are consumed
Solution Approach 1:
The patent utilizes the vertical dimension of the 3-dimensional memory structure by forming conductor-filled trenches that extend through multiple levels of the staircase structure. This allows signal routing to occur in the vertical direction rather than consuming additional horizontal silicon real estate, effectively transitioning from 2D to 3D routing space utilization.
Solution Approach 2:
The conductor-filled trenches are nested within the staircase structure, with the trenches passing through multiple levels and steps of the 3-dimensional array. This nesting approach allows multiple routing functions to be integrated within the existing structural footprint, eliminating the need for additional external conductors.
2Ease of operation
If additional conductors are added to access bit lines and source lines, then signal routing is improved, but conductor resources are depleted
Solution Approach 1:
The conductor-filled trenches serve multiple functions simultaneously: they provide electrical connection between different levels, act as signal routing pathways, and integrate with the staircase structure to access both bit lines and source lines. This multi-functionality eliminates the need for separate dedicated conductors for each routing function.
Solution Approach 2:
The patent merges the routing function with the existing staircase structure by forming trenches that pass through the steps. The conductors within these trenches combine multiple routing paths into a single integrated structure, reducing the total number of separate conductors required.
3Ease of operation
If more silicon real estate is allocated for routing, then signal access is improved, but device area increases
Solution Approach 1:
The invention transitions signal routing from the horizontal plane to the vertical dimension by forming trenches that extend through the stacked levels of the staircase structure. This allows comprehensive signal access to all levels without expanding the horizontal device footprint, effectively utilizing the third dimension for routing space.
Solution Approach 2:
The staircase structure provides dynamic access to different levels through the conductor-filled trenches, allowing selective connection to various bit lines and source lines at different heights. This dynamic routing capability is achieved within the existing vertical footprint without requiring additional horizontal space.
Data Source
AI summary
A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.