3D Memory Via Routing Through Dielectric Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional memory devices require complex and costly processes to form via structures through entire word line stacks, consuming significant area and increasing processing costs, while underutilizing dielectric filled areas.
Innovation Solution
The formation of via structures in dielectric filled bit line break areas and free staircase regions within the word line stack, utilizing underutilized dielectric material for increased device density and simplifying processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via structures are formed through entire word line stacks, then electrical connection is achieved, but device area is consumed and processing cost increases
Solution Approach 1:
The patent changes the routing dimension from vertical (through the entire stack) to lateral (through dielectric regions at specific levels). Bit lines and power lines are routed laterally through dielectric regions between memory stacks, avoiding vertical penetration through the full stack height. This dimensional change reduces area consumption while maintaining electrical connection reliability.
Solution Approach 2:
The patent segments the interconnect routing into separate functional layers: bit lines at bit-line-level, power lines at power-line-level, and word line connections at word-line-connection level. Each segment is routed through appropriate dielectric regions at its designated level, eliminating the need for a single complex through-stack via structure and reducing overall area requirements.
2Reliability
If via structures extend through entire word line stacks, then electrical connection is achieved, but processing complexity and cost increase
Solution Approach 1:
The patent divides the interconnect system into separate segmented lines: bit-line-level bit lines, power-line-level power lines, and word-line-connection lines. Each segment is formed independently through targeted etching and filling of dielectric regions at specific levels, rather than forming a single complex through-stack via. This segmentation simplifies processing steps and reduces manufacturing complexity.
Solution Approach 2:
The patent introduces dielectric regions as intermediary routing channels at specific levels within the stack. These dielectric regions serve as mediators that allow lateral routing of bit lines and power lines without requiring vertical penetration through the entire stack. The intermediary dielectric pathways simplify the formation process compared to direct through-stack via creation.
3Reliability
If conventional via formation processes are used, then electrical connection is achieved, but dielectric material utilization is underoptimized
Solution Approach 1:
The patent makes dielectric regions multi-functional by using them both as structural support material and as routing channels for interconnect lines. The same dielectric regions that provide mechanical support and electrical isolation also serve as the medium through which bit lines, power lines, and word line connections are routed laterally. This universal utilization maximizes the functional value of dielectric material in the device architecture.
Solution Approach 2:
The patent transforms underutilized dielectric material into functional routing channels by introducing lateral pathways at specific levels within the stack. Instead of leaving dielectric regions as passive fill material, the invention creates horizontal conduits through these dielectric regions for signal and power distribution, thereby optimizing material utilization and adding functional capability.
Data Source
AI summary
A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions. Metal line structures connecting contact via structures can extend parallel to bit lines to provide electrical connections between word lines and underlying field effect transistors.