3D Memory Via Formation Using Sacrificial Layer Etching
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Solution Overview
Problem
Current methods for creating three-dimensional memory devices with through-array contact via structures are costly and time-consuming, as they require complex processing steps and high precision to avoid contact between dielectric wall structures.
Innovation Solution
A three-dimensional memory device design featuring field effect transistors over a semiconductor substrate with lower-level metal interconnect structures, an alternating stack of insulating and composite layers, and dielectric spacer plates, allowing for the formation of conductive via structures through the stack without direct contact between dielectric wall structures, using a method that includes forming sacrificial material layers, patterning, and isotropic etching to create backside recesses and electrically conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex processing steps are used to form through-array contact via structures, then manufacturing precision is improved, but processing time increases and manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by forming the alternating stack of insulating layers and sacrificial material layers before forming the through-array contact via structures. The sacrificial material layers are pre-positioned to define future via locations, and the alternating stack is prepared in advance with precisely controlled layer thicknesses and patterns. This preliminary preparation enables subsequent via formation to proceed more quickly without sacrificing precision, as the structural framework is already in place to guide the contact via creation process
Solution Approach 2:
The patent segments the through-array contact via formation process into distinct stages: (1) forming the alternating stack with sacrificial material layers, (2) creating openings through the alternating stack, (3) removing sacrificial material to define via regions, and (4) forming conductive via structures. This segmentation allows each step to be optimized independently, reducing overall processing time while maintaining precision through systematic progression rather than attempting complex single-step formation
2Reliability
If dielectric wall structures are formed to prevent contact between alternating stacks, then reliability is improved, but device complexity increases
Solution Approach 1:
The alternating stack structure itself serves multiple functions: it provides electrical isolation between adjacent stacks through the insulating layers, defines the geometric pattern for contact via formation through the sacrificial material layers, and creates the structural framework for subsequent via processing. This multi-functionality eliminates the need for separate dielectric wall structures, as the alternating stack components perform both the isolation and the via-definition roles simultaneously, reducing overall device complexity while maintaining reliability
Solution Approach 2:
The patent merges the functions of isolation structures and via-definition structures into the alternating stack itself. The insulating layers provide isolation between stacks, while the sacrificial material layers simultaneously define where vias should be formed. By combining these functions into a single integrated structure rather than using separate dielectric wall structures, the patent reduces device complexity while ensuring reliable isolation between alternating stacks
3Manufacturing precision
If high precision processing is used to avoid contact between dielectric wall structures, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses sacrificial material layers that are intentionally designed to be removed after serving their temporary purpose of defining via locations. These sacrificial layers are formed with precise patterns to guide via formation, then selectively removed to create openings. This disposable approach allows for precise via placement without requiring expensive, permanent dielectric wall structures, as the sacrificial materials serve their function and are then discarded, reducing manufacturing cost while maintaining precision
Solution Approach 2:
The sacrificial material layers act as intermediary structures that temporarily define via locations during processing. These intermediaries are formed with precise patterns, guide the subsequent via formation process, and then are removed once their defining function is complete. This intermediary approach enables precise contact via formation without requiring expensive permanent isolation structures, as the sacrificial materials serve as temporary guides that are then discarded, reducing manufacturing cost while maintaining precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing costs and time by enabling efficient formation of interconnects through the memory stack without direct contact between dielectric wall structures, improving the manufacturing efficiency of three-dimensional memory devices.
Implementation Method 1
forming backside recesses by isotropically etching portions of the sacrificial material layers of the plurality of alternating stacks selective to the insulating layers of the plurality of alternating stacks by introducing an isotropic etchant into the backside trenches
Implementation Method 2
wherein the barrier trenches are covered by a respective dielectric liner that blocks access of the isotropic etchant to adjacent portions of the sacrificial material layers
Data Source
AI summary
An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.