3D Memory Mold Structure with Through-Via Stress Relief
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by cost and manufacturing factors, particularly in two-dimensional devices, while three-dimensional devices offer increased density but face challenges in maintaining product reliability due to stress on mold structures.
Innovation Solution
A semiconductor memory device design featuring a mold structure with alternately stacked insulation films and gate electrodes, channel structures penetrating through, and strategically placed through vias to reduce stress and enhance reliability, along with a method for fabricating these devices that includes forming block separation regions and dam regions to manage stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor memory devices are used to increase integration density, then the degree of integration is improved, but stress on mold structures increases reducing product reliability
Solution Approach 1:
The mold structure is divided into multiple segments by introducing through vias that penetrate through the stacked layers. These through vias act as stress relief points, segmenting the continuous mold structure into discrete regions that can independently accommodate thermal expansion and mechanical stress, thereby preventing catastrophic failure while maintaining high integration density
Solution Approach 2:
Different regions of the mold structure are given different properties by strategically placing through vias in specific locations where stress concentration occurs. The through vias create local stress relief zones without compromising the overall structural integrity, allowing the mold to maintain strength in critical areas while providing stress relief in high-stress regions
2Productivity
If two-dimensional semiconductor memory devices are miniaturized to increase integration, then the degree of integration is improved, but manufacturing cost increases due to expensive apparatuses required
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. By stacking multiple layers of insulation films and gate electrodes alternately, the device achieves higher integration density without requiring advanced fine pattern forming technology, thereby avoiding the need for expensive miniaturization apparatuses
Data Source
AI summary
A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.