3D Vertical Memory Off-Die Voltage Generator Segmentation
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Solution Overview
Problem
Integrated three-dimensional vertical memory (3D-MV) devices face increased costs and performance degradation due to the need for expensive BEOL manufacturing processes and limited peripheral circuit optimization, as the integration of 3D-MV arrays and peripheral circuits requires using the same manufacturing processes, leading to inefficient use of resources and reduced performance.
Innovation Solution
Separating the 3D-MV array and voltage generator into different dice allows for optimized BEOL structures and materials, enabling lower-cost production and improved performance by using fewer and faster interconnect levels in the voltage-generator die, while maintaining efficient memory cell density in the 3D-array die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If integrated 3D-MV design is used to combine memory arrays and peripheral circuits on a single die, then device integration is improved, but manufacturing cost increases and performance degrades due to incompatible BEOL processes
Solution Approach 1:
The patent divides the 3D-MV device into separate components: a 3D-array die containing the memory array and a voltage-generator die containing the peripheral circuits. This segmentation allows each component to be manufactured using optimized, compatible processes while maintaining functional integration through stacking, thereby reducing manufacturing cost despite maintaining device integration.
2Device complexity
If integrated 3D-MV design is used to combine memory arrays and peripheral circuits on a single die, then device integration is improved, but peripheral circuit performance degrades due to limited BEOL levels
Solution Approach 1:
By separating peripheral circuits into a dedicated voltage-generator die with its own optimized BEOL structure, the patent enables higher-performance circuit design without being constrained by the memory array's BEOL limitations. The stacked configuration maintains integration while allowing each component to operate at its optimal performance level.
3Ease of manufacture
If discrete 3D-MV design is used to separate 3D-array die and voltage-generator die, then manufacturing cost decreases and performance improves through optimized BEOL structures, but device integration decreases
Solution Approach 1:
The patent implements vertical stacking where the voltage-generator die is positioned beneath the 3D-array die, creating a nested three-dimensional structure. This nesting maintains high device integration and compact form factor while allowing each die to have independently optimized BEOL structures for its specific manufacturing requirements and performance characteristics.
Data Source
AI summary
The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a voltage-generator die. The 3D-array die comprises a plurality of vertical memory strings. At least a voltage generator for the 3D-array die is located on the voltage-generator die instead of the 3D-array die. The 3D-array die and the voltage-generator die have substantially different back-end-of-line (BEOL) structures.