3D Memory Controller Layer Voltage Selection

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Solution Overview

Problem

Three-dimensional memory constructs face reliability and accuracy issues due to manufacturing inconsistencies and complex trace routing, leading to reduced performance in read and write operations.

Innovation Solution

A controller is configured to select reference voltages based on the layer of memory cells within a three-dimensional memory construct, adapting to manufacturing imperfections by using discrete reference voltages corresponding to specific conditions such as retention time and program erase cycles, to improve the accuracy and reliability of memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensional memory constructs are used to increase memory density, then storage capacity is improved, but manufacturing inconsistencies and trace routing complexity increase leading to reduced read/write accuracy

Engineering Contradiction:
Improvememory densityVSAvoidread/write accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent applies local quality by assigning different reference voltage offsets to different layers of the three-dimensional memory construct. Each layer receives a customized reference voltage based on its specific manufacturing characteristics and trace routing properties, rather than using a uniform reference voltage for all layers. This layer-specific voltage adjustment compensates for local variations in threshold voltages caused by manufacturing inconsistencies, thereby improving read/write accuracy while maintaining high memory density.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If advanced manufacturing techniques are used to reduce memory cost, then production efficiency is improved, but reliability and speed deteriorate

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmemory reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs parameter changes by dynamically adjusting the reference voltage offset parameter for each layer based on manufacturing data and operational conditions. The memory controller modifies the reference voltage to compensate for variations introduced by advanced manufacturing techniques, thereby maintaining reliable read/write operations despite the use of cost-effective, high-volume manufacturing processes. This allows production efficiency to be improved without sacrificing memory reliability.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If advanced manufacturing techniques are used to reduce memory cost, then production efficiency is improved, but speed deteriorates

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmemory speed
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent applies preliminary action by pre-characterizing each layer during manufacturing or initial operation to determine the optimal reference voltage offset for that layer. This characterization data is stored and used during subsequent read/write operations to quickly compensate for manufacturing variations. By performing the voltage optimization work in advance, the system achieves fast read/write speeds comparable to uniformly manufactured memory, while still benefiting from the cost and production efficiency advantages of advanced manufacturing techniques.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10262744B2Layer-based memory controller optimizations for three dimensional memory constructs
Publication Date: 2019.04.16 SK HYNIX INC
  • US10262744B2 patent drawing
  • US10262744B2 patent drawing
  • US10262744B2 patent drawing

AI summary

Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. The memory cell can be a flash memory cell.