3D Embedded Memory Wafer Bonding for High-Bandwidth Access
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Solution Overview
Problem
Conventional DRAM arrays are limited by their 2-dimensional structure, sharing silicon real estate with support circuitry, leading to lower density and capacity compared to 3-D NOR memory arrays, and face bandwidth limitations due to pin constraints and high power consumption in signal transfer.
Innovation Solution
A high-bandwidth, high-capacity memory device is created by wafer-bonding a memory circuit with a logic circuit, using modular memory units in a 3-D array, allowing flexible interconnects through studs or TSVs, and incorporating quasi-volatile memory (QVM) with fast access and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM arrays use 2-dimensional structure, then manufacturing is simpler, but memory density and capacity are limited
Solution Approach 1:
The patent transitions from conventional 2-dimensional DRAM arrays to 3-dimensional memory structures by stacking multiple memory layers vertically. This dimensional change enables significantly higher memory density and capacity while maintaining compatibility with existing manufacturing processes through techniques like through-silicon vias (TSVs) and wafer bonding.
2Productivity
If signal transfer uses conventional pin connections, then device fabrication is simpler, but bandwidth is limited and power consumption increases
Solution Approach 1:
The patent extracts the signal transfer function from conventional pin connections and implements it through integrated through-silicon via (TSV) connections within the 3D stacked structure. This extraction enables shorter signal paths, higher bandwidth, and reduced power consumption by eliminating the need for external pin connections and reducing signal transmission distance.
3Adaptability or versatility
If wafer bonding is used to connect memory and logic circuits, then integration and bandwidth are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory system into separate memory circuit wafers and logic circuit wafers that can be independently fabricated and then bonded together using wafer bonding technology. This segmentation provides manufacturing flexibility and adaptability while managing complexity through modular assembly, allowing different process technologies to be used for memory and logic portions.
Data Source
AI summary
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having at least a three-dimensional array of storage transistors, and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit includes numerous modular memory support circuits. The first and second semiconductor dies are electrically connected by bonding pads formed on each semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.