3D Memory Cell Stacking With Wafer Bonding for Low Parasitic Capacitance
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Solution Overview
Problem
Existing 3D memory devices face challenges in achieving high integration and reduced parasitic capacitance to meet the demands of large capacity and miniaturization.
Innovation Solution
A method involving epitaxial growth of semiconductor layers and a wafer bonding process is used to form a three-dimensional memory cell array with vertically stacked memory cells, incorporating a bonding structure and vertical conductive lines to enhance integration and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase capacity, then storage density is improved, but parasitic capacitance increases
Solution Approach 1:
The memory device is divided into multiple stacked layers with bonding structures separating them. Each layer contains memory cells that can be independently managed, allowing the device to achieve high density while the bonding structures help manage and reduce parasitic capacitance between layers through optimized electrical isolation and connection paths.
2Manufacturing precision
If wafer bonding process is used to stack mold stacks, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Mold stacks are prepared and pre-assembled with bonding layers formed in advance on separate substrates. The preliminary formation of bonding layers and mold stack structures allows for precise alignment to be achieved during the final bonding process, while the pre-preparation reduces the complexity of in-situ alignment during fabrication.
3Manufacturing precision
If epitaxial growth is used to form semiconductor layers, then manufacturing precision is improved, but production time increases
Solution Approach 1:
The epitaxial growth process utilizes parameter optimization including temperature, pressure, and gas flow control to achieve precise layer thickness and composition. By carefully adjusting these parameters, high manufacturing precision is achieved while minimizing growth time through efficient deposition rates and process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high memory cell density and reduces parasitic capacitance, improving the performance characteristics of 3D memory devices.
Implementation Method 1
performing a wafer bonding process using the first bonding layer and the second bonding layer to form a mold stack with a high stack including the first mold stack and the second mold stack
Implementation Method 2
forming a first mold stack including first and second mold layers epitaxially grown on a substrate
Data Source
AI summary
A semiconductor device may include high-integrated memory cells, and a method for fabricating the semiconductor device may include forming a first mold stack and a first bonding layer on a substrate; forming a second mold stack and a second bonding layer on a sacrificial substrate; flipping the sacrificial substrate and bonding the first and second bonding layers; removing the sacrificial substrate; and forming a plurality of memory cells vertically stacked in the first and second mold stacks.