3D Memory Wafer Bonding to Prevent CMOS Plasma Damage
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to process technology limitations, leading to an upper limit in memory density, and conventional 3D memory fabrication methods risk damaging CMOS devices during through silicon contact etching.
Innovation Solution
A 3D memory device fabrication method involving separate formation of array and CMOS wafers, flipped for hybrid bonding, with an alternating dielectric etch stop structure and vertical through contacts to avoid plasma damage, and simultaneous formation of interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D memory fabrication methods are used with through silicon contact etching, then vertical interconnects can be formed, but CMOS devices are damaged by plasma
Solution Approach 1:
The fabrication process is divided into separate sequence: array wafer formation, CMOS wafer formation, hybrid bonding, and then through substrate contact formation. This segmentation allows the CMOS wafer to be formed and protected before the plasma etching step, eliminating plasma damage while maintaining vertical interconnect functionality.
Solution Approach 2:
The CMOS wafer is formed and bonded to the array wafer before the through substrate contact etching process. This preliminary action ensures that CMOS devices are already in place and protected by the array wafer structure, preventing plasma exposure and damage during the subsequent etching step.
2Quantity of substance
If planar memory cell scaling is continued, then memory density increases, but process technology becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell scaling to three-dimensional stacked architecture. Memory cells are arranged vertically across multiple layers and wafers, enabling continued density increase without further lateral scaling. This dimensional change avoids the process technology challenges and costs associated with sub-10nm planar scaling.
Solution Approach 2:
Multiple memory layers are stacked vertically with each layer containing memory cells, control gates, and interconnect structures nested within the three-dimensional space. The array wafer and CMOS wafer are bonded together, creating a nested configuration that maximizes memory density within the vertical dimension.
3Reliability
If separate array and CMOS wafers are formed and bonded, then plasma damage is avoided, but device complexity increases
Solution Approach 1:
The array wafer serves as an intermediary protective layer between the plasma etching process and the CMOS wafer. During through substrate contact formation, the array wafer absorbs and protects the CMOS devices from plasma exposure, enabling the separate wafer approach without excessive complexity.
Solution Approach 2:
The array wafer and CMOS wafer are merged through hybrid bonding, creating an integrated three-dimensional memory device. This merging combines the benefits of separate formation (plasma protection) with the functionality of an integrated device, managing complexity through standardized bonding interfaces and processes.
Data Source
AI summary
A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an etch stop structure in a first wafer, forming a first through contact in contact with the etch stop structure, bonding the first wafer to a second wafer to electrically connect the first through contact to a CMOS device of the second wafer, and forming a through substrate contact penetrating a first substrate of the first wafer and the etch stop structure, and in electrically contact with the CMOS device through the first through contact.