3D Memory Device Wafer Bonding for Density
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Solution Overview
Problem
The challenge in designing and fabricating 3D NAND memory devices lies in the shrinking CMOS area required for increasing 3D NAND layers, which complicates the integration of peripheral devices and increases costs, as traditional planar memory cell fabrication techniques reach their limits in terms of density and complexity.
Innovation Solution
A method involving the stacking of a memory array wafer and a CMOS wafer with HV, LV, and LLV circuitry, where the CMOS wafer includes page buffer regions, and the wafers are bonded at a specific interface to form a 3D memory device, allowing for separate formation and optimization of high and low-voltage circuitry in distinct semiconductor layers, reducing the total area occupied by memory peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of 3D NAND layers is increased to improve memory density, then the memory array size decreases, but the CMOS area required for peripheral devices also shrinks, making integration challenging
Solution Approach 1:
The patent divides the CMOS peripheral devices into multiple separate CMOS areas (first CMOS area, second CMOS area, third CMOS area) distributed across different substrates. The first and second CMOS areas are formed on a first substrate, while the third CMOS area is formed on a second substrate. This segmentation allows each CMOS area to be independently optimized and integrated, reducing overall integration complexity while maintaining high memory density.
Solution Approach 2:
The patent transitions from a planar 2D layout to a 3D stacked architecture where memory arrays and CMOS peripheral devices are vertically integrated across multiple substrates. The memory array is formed between the first and second substrates, while CMOS areas are distributed on both substrates. This dimensional change enables higher density without proportionally reducing CMOS area, as the CMOS devices utilize the lateral space on substrate surfaces rather than competing for the same planar area.
2Adaptability or versatility
If multiple CMOS areas are used to accommodate peripheral devices, then the integration flexibility increases, but the fabrication complexity and costs increase
Solution Approach 1:
The patent segments CMOS peripheral devices into multiple independent CMOS areas located on different substrates. Each CMOS area can be independently fabricated, tested, and integrated, providing design flexibility while allowing parallel fabrication processes that may reduce overall manufacturing complexity and cost.
Solution Approach 2:
The patent creates a modular architecture where multiple CMOS areas with similar functional blocks (string drivers, page buffers, sense amplifiers) are distributed across substrates. These modular units can be independently fabricated using standardized processes and then integrated, providing universality in the fabrication approach and reducing the need for custom fabrication for each peripheral device type.
3Ease of manufacture
If planar memory cell fabrication techniques are used to improve manufacturing process, then the fabrication cost decreases, but the memory density approaches an upper limit
Solution Approach 1:
The patent employs a 3D stacked memory architecture where memory cells are arranged vertically between first and second substrates, with word lines extending in the vertical direction. This three-dimensional arrangement dramatically increases memory density compared to planar 2D layouts, while the modular CMOS integration approach maintains fabrication efficiency by using distributed, independently-fabricated peripheral device areas.
Data Source
AI summary
A method for forming a 3D memory device includes forming an array wafer having a memory array layer and a CMOS layer stacked together, including: forming the CMOS layer having HV circuitry of a plurality of peripheral devices, and forming a plurality of memory cells and a string structure in the memory array layer. The memory array layer includes at least one cell region for forming the memory cells and at least one string structure region for forming the string structure, and the CMOS layer includes at least one string driver region. The method also includes forming a CMOS wafer having LV circuitry and LLV circuitry of the plurality of peripheral devices, the CMOS wafer including at least one page buffer region; bonding the array wafer and the CMOS wafer at a bonding interface; and forming the 3D memory device based on the bonded array wafer and CMOS wafer.