3D Memory Device Wafer Bonding for Reduced Fabrication Complexity
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Solution Overview
Problem
The fabrication process of multi-stack 3D NAND memory devices is complex and requires improvement, particularly in simplifying the process and reducing the size of the device while maintaining uniformity and reducing the number of sacrificial layers and high aspect-ratio semiconductor channels.
Innovation Solution
A method involving the bonding of two wafers with staircase structures and semiconductor channels, where sacrificial layers are minimized, and semiconductor channels are formed by aligning and adjoining sub-channels from each wafer, allowing for the formation of gate electrodes and peripheral devices before bonding, and via structures are formed post-bonding to connect these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple stacks of staircase structures are arranged along the direction perpendicular to the substrate to increase memory cell density, then the storage capacity is improved, but the fabrication process complexity increases and device size increases
Solution Approach 1:
The patent divides the fabrication process into two separate wafers: a first wafer for forming staircase structures and a second wafer for forming dielectric stacks. This segmentation allows independent optimization of each structure type and simplifies the overall fabrication process by avoiding the need to form both structures on a single substrate simultaneously.
Solution Approach 2:
The patent forms semiconductor channels that extend through multiple stacked structures (staircase structures and dielectric stacks) in a nested arrangement. The channels are formed to pass through alternating layers of sacrificial material and insulating material, creating a nested configuration where channels are embedded within multiple hierarchical structure levels.
2Length of stationary object
If high aspect ratio etches are used to form deep semiconductor channels, then vertical integration is improved, but substrate over etch occurs and manufacturing precision deteriorates
Solution Approach 1:
The patent forms sacrificial layers and insulating layers in alternating stacked structures before forming the semiconductor channels. These pre-formed layers serve as etch stops and guides during channel formation, preventing substrate over etch while enabling the formation of deep vertical channels with precise depth control.
Solution Approach 2:
The patent uses sacrificial material layers as intermediary structures during channel formation. These sacrificial layers are deposited between the insulating layers and are selectively removed or used as etch masks to define the semiconductor channel regions, enabling precise channel formation without direct substrate over etching.
3Quantity of substance
If the number of sacrificial layers is increased to form more staircase structures, then storage capacity is improved, but fabrication complexity and process time increase
Solution Approach 1:
The patent combines the formation of multiple staircase structures and dielectric stacks into a single integrated fabrication process on two wafers. By merging these structures and subsequently bonding the wafers, the patent achieves high storage capacity without proportionally increasing fabrication time, as the structures are formed simultaneously rather than sequentially.
Solution Approach 2:
The patent transitions from forming structures on a single planar substrate to a three-dimensional stacked configuration by bonding two wafers together. This dimensional change allows multiple staircase structures and dielectric stacks to be arranged vertically, increasing storage capacity without proportionally increasing the lateral fabrication area or process time.
Data Source
AI summary
Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure.