3D Memory Structure Using Low-Shrinkage Insulators to Limit Warpage
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Solution Overview
Problem
Existing semiconductor memory devices face issues with manufacturing warpage due to thermal shrinkage of insulating materials, leading to potential electrical connectivity failures and increased manufacturing processes.
Innovation Solution
The semiconductor memory device incorporates a structure body and support member made of polycrystalline silicon and silicon oxide, which reduces thermal shrinkage stress, and includes a metal layer to enhance rigidity and heat resistance, allowing for simultaneous formation with other components and enabling post-manufacturing inspection for short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating materials are used in the semiconductor memory device, then electrical insulation is provided, but thermal shrinkage occurs during manufacturing causing warpage
Solution Approach 1:
The patent changes the material parameter from conventional insulating materials to low-thermal-shrinkage materials (LTSM), specifically mentioning materials with thermal shrinkage rates of 0.1% or less. This parameter change directly addresses the warpage issue while maintaining the electrical insulation function.
Solution Approach 2:
The patent employs composite material structures, particularly the gate insulating film composed of multiple layers including silicon oxide and silicon nitride, and the inter-string unit insulating layers using LTSM. These composite structures provide both electrical insulation and thermal stability, resolving the contradiction between insulation and warpage prevention.
2Manufacturing precision
If additional manufacturing processes are implemented to prevent warpage, then manufacturing precision is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent applies preliminary action by selecting and preparing low-thermal-shrinkage materials before the manufacturing process begins. The materials are pre-characterized for their thermal shrinkage properties, allowing the warpage issue to be prevented from the outset rather than requiring corrective processes during or after manufacturing.
Solution Approach 2:
By changing the material parameter to LTSM with controlled thermal shrinkage rates, the patent eliminates the need for additional warpage correction processes. This parameter change simplifies the manufacturing workflow while maintaining high precision.
3Ease of manufacture
If conventional insulating materials are used, then manufacturing is simpler, but electrical connectivity failures occur due to warpage
Solution Approach 1:
The patent uses composite material structures where LTSM layers are combined with conductive layers and semiconductor structures. This composite approach maintains manufacturing simplicity while ensuring reliable electrical connectivity by preventing warpage-induced connection failures.
Solution Approach 2:
The patent changes the thermal shrinkage parameter of the insulating materials to LTSM specifications, which maintains ease of manufacture through standard deposition processes while dramatically improving electrical connectivity reliability by eliminating warpage-related failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes warpage, ensures reliable electrical connections, reduces manufacturing complexity, and maintains high quality by allowing for efficient inspection and prevention of short circuits.
Implementation Method 1
includes a metal layer to enhance rigidity and heat resistance
Implementation Method 2
incorporates a structure body and support member made of polycrystalline silicon and silicon oxide, which reduces thermal shrinkage stress
Data Source
AI summary
A semiconductor memory device includes a substrate that includes a first region and a second region. The first region includes: a plurality of first word line layers; a first semiconductor layer having an outer peripheral surface opposed to the plurality of first word line layers; and a first electric charge accumulating film disposed between the plurality of first word line layers and the first semiconductor layer. The second region includes: a part of the plurality of first word line layers; a plurality of first insulating layers, the plurality of first insulating layers; a first contact having an outer peripheral surface opposed to the plurality of first insulating layers; a second semiconductor layer disposed between the plurality of first word line layers and the plurality of first insulating layers; and a second electric charge accumulating film disposed between the plurality of first insulating layers and the second semiconductor layer.