3D Memory Block Layout for Warpage-Resistant Semiconductor Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and achieving high degrees of integration and reliability, particularly in minimizing warpage to prevent defects and enhance performance.
Innovation Solution
The semiconductor device design includes first and second conductive plate structures with memory blocks and separation structures arranged in perpendicular horizontal directions, minimizing warpage and allowing for increased stacking of word lines, which improves integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple memory blocks vertically. Multiple conductive plate structures are positioned at different vertical levels, with word lines extending through multiple stacks, enabling increased storage capacity through vertical dimension exploitation.
Solution Approach 2:
The patent implements nested structures where bit lines are formed within trenches that extend through multiple memory blocks. The bit line structure is nested within the vertical stack, with insulating layers and conductive materials arranged in concentric or nested configurations to achieve compact three-dimensional integration.
2Productivity
If more word lines are stacked to increase integration degree, then integration is improved, but warpage occurs causing defects
Solution Approach 1:
The patent divides the conductive plate structures into multiple separate stacks positioned at different vertical levels. Each stack is separated by insulating layers, preventing continuous stress accumulation. The word lines are also segmented into multiple sets (first, second, third word lines) at different vertical positions, allowing independent stress management and reducing overall warpage.
Solution Approach 2:
The patent introduces insulating layers between adjacent conductive plate structures and between different word line sets. These insulating layers act as intermediaries that electrically isolate and mechanically decouple the stacked structures, preventing stress transmission that would cause warpage while maintaining electrical connectivity through vertical contacts.
Data Source
AI summary
A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.