3D Memory Wiring Layer Layout for Lower Noise and Congestion
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively laying out wirings to reduce noise, resistance, and enhance speed, particularly in three-dimensional memory designs where congestion and noise interference are significant.
Innovation Solution
The semiconductor device incorporates a wiring layer that is positioned above the substrate, electrically connected to the memory cell, and formed from the same wiring layer as the bonding pad, allowing for reduced congestion and noise interference while simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wirings are laid out in conventional layers, then manufacturing process is simplified, but wiring congestion and noise interference increase
Solution Approach 1:
The patent applies dimensionality change by forming wirings above the substrate surface using a wiring layer, transitioning from conventional planar wiring layout to a three-dimensional configuration. This allows wirings to be positioned in the vertical dimension (Z-axis) rather than only in the horizontal plane, thereby reducing wiring congestion and noise interference while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
2Object-affected harmful factors
If wiring layer is positioned above substrate, then wiring congestion and noise are reduced, but device thickness increases
Solution Approach 1:
The patent utilizes vertical space above the substrate by forming wirings in the Z-direction using a wiring layer, effectively distributing wiring routes in three dimensions. This dimensional transition reduces the need for extensive planar wiring, thereby minimizing wiring congestion and noise while the overall thickness increase is managed through optimized layer configuration and compact vertical stacking.
3Adaptability or versatility
If separate wiring layer is added above substrate, then wiring flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of the wiring layer with existing semiconductor manufacturing processes, integrating wiring formation into the standard fabrication sequence. By combining wiring layer deposition, patterning, and etching steps with conventional process flows, the patent achieves enhanced wiring layout flexibility without significantly increasing manufacturing complexity, as the wiring layer is formed using established semiconductor fabrication techniques.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.