3D Resistive Memory Computing Circuit Without Detection Amplifiers
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Solution Overview
Problem
Existing non-volatile memory technologies for in-memory computing face challenges such as increased circuit complexity, power consumption, and reduced computational performance due to the use of large peripheral circuits and limitations in stacking memory cells, especially when executing parallel computation algorithms.
Innovation Solution
A three-dimensional structure of resistive, non-volatile, and programmable memory cells with specific programming sequences for elementary logic functions and data transfer, reducing peripheral circuit complexity and enabling parallel data processing without the need for detection amplifiers, and allowing operation in three spatial dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large peripheral circuits (detection amplifiers) are used to process computation results in memory, then computation accuracy is improved, but circuit area and complexity increase significantly
Solution Approach 1:
The patent extracts and eliminates the detection amplifier circuits from the memory computing architecture. Instead of using traditional detection amplifiers to process computation results, the invention uses a simplified readout mechanism where the computation results are directly read from the memory cells through selective word line activation, removing the complex peripheral processing circuits while maintaining computational accuracy through the inherent properties of the resistive memory crossbar structure.
Solution Approach 2:
The memory computing circuit performs self-reading of computation results without external detection amplifiers. The crossbar architecture inherently provides the necessary signal isolation and selection through its structure, where activating specific word lines automatically selects the relevant computation results for reading, making the system self-sufficient and eliminating the need for complex external processing circuits.
2Measurement precision
If detection amplifier circuits are used to process computation results, then computation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-hungry detection amplifier circuits from the architecture. The simplified readout mechanism uses minimal power by directly reading computation results through selective word line activation, eliminating the continuous power consumption associated with operating detection amplifiers while maintaining the ability to accurately read computation results when needed.
Solution Approach 2:
The readout operation is performed periodically and selectively rather than continuously. Detection amplifiers are activated only when computation results need to be read, and even then only for specific word lines that contain the required data. This periodic, on-demand activation significantly reduces overall power consumption compared to keeping detection amplifiers continuously operational.
3Area of stationary object
If memory cells are stacked in a single elementary structure with common FinFET transistor, then integration density is improved, but the number of stackable memories is limited due to increased loss currents
Solution Approach 1:
The patent segments the memory structure into multiple independent crossbar arrays rather than stacking memories with a common FinFET transistor. Each crossbar array operates independently with its own set of bit lines and word lines, allowing for better current isolation. This segmentation prevents the accumulation of loss currents that would occur in a stacked configuration with shared transistors, enabling higher integration density through lateral expansion of multiple independent arrays rather than vertical stacking with common control.
4Device complexity
If operand and result storage are constrained to the same elementary structure, then circuit simplicity is improved, but programmability and computational performance are reduced
Solution Approach 1:
The patent implements a universal crossbar architecture where the same memory cells can serve multiple functions: storing operands, storing intermediate results, and storing final outputs. The flexible word line activation mechanism allows any row of memory cells to be selected for reading or writing, enabling the system to perform various computational operations and algorithms without being constrained by fixed operand-result positioning. This multi-functionality greatly enhances programmability while maintaining circuit simplicity through the uniform crossbar structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces circuit area and power consumption, enhances programming flexibility, and supports the execution of complex computational algorithms with improved performance by allowing a greater number of memory cells and parallel operations, while being compatible with semiconductor manufacturing techniques.
Implementation Method 1
The control means are configured to apply a predetermined sequence of electrical voltages to the nodes of the memory cells of said elementary group so as to obtain a voltage divider to perform the first logical operation
Data Source
Figure 1a~1b
Figure 2a
Figure 2b
AI summary
The invention relates to a memory computing circuit comprising a plurality of memory planes. Each plane forms a two-dimensional matrix of non-volatile, resistive, and programmable memory cells. Each memory cell has a selection node, a first input/output node, and a second input/output node. Said computing circuit comprises at least one elementary group of memory cells including: - a first memory cell belonging to any one of the memory planes and intended to store a first input data item; - a second memory cell belonging to any one of the memory planes and intended to store a second input data item; - a third memory cell belonging to a memory plane different from that of the first and second memory cells, the third memory cell being intended to store the result of a first logical operation having as operands the first and second input data items.