3D Memory Word Line Grouping via Multi-Layer Conductive Wiring
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Solution Overview
Problem
The complexity of circuit layouts in three-dimensional memory devices, particularly in word line signal transmission paths, leads to increased capacitance and resistance, which hampers high-speed access and signal transmission quality.
Innovation Solution
The word lines are divided into groups and connected through multiple conductive wire layers, with switches receiving common word line and reference ground voltages, reducing layout complexity and capacitance load by optimizing the transmission path layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If word lines are connected through a single conductive wire layer, then the layout is simpler, but the transmission path length increases leading to higher capacitance and resistance
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional multi-layer conductive wire structure. Word lines are distributed across multiple conductive wire layers (first, second, and third layers), with vertical connections through via holes. This dimensional change allows shorter horizontal transmission paths while maintaining electrical connectivity, thereby reducing capacitance and resistance without increasing layout complexity.
2Reliability
If word lines are divided into multiple groups connected through multiple conductive wire layers, then capacitance load and resistance are reduced, but the layout becomes more complicated
Solution Approach 1:
The patent segments the word lines into multiple groups (first word line group, second word line group, third word line group, etc.) and distributes them across different conductive wire layers. Each group is connected to switch drivers through dedicated transmission paths in specific layers. This segmentation reduces the capacitance load on each transmission path and minimizes resistance by shortening individual path lengths, while the modular grouping approach actually simplifies the overall layout organization.
Solution Approach 2:
By utilizing multiple conductive wire layers stacked vertically, the patent creates a three-dimensional wiring architecture. This allows word line groups to be connected through vertical via holes rather than long horizontal traces, significantly reducing transmission path length and electrical parasitics. The multi-layer approach organizes complex connections in the vertical dimension, making the horizontal layout cleaner and more manageable.
3Productivity
If transmission path length is reduced, then capacitance and resistance decrease improving access performance, but the area required for multi-layer connections increases
Solution Approach 1:
The patent exploits the vertical dimension by implementing multiple conductive wire layers stacked above each other. Transmission paths are shortened by routing signals vertically through via holes between layers rather than horizontally across the chip surface. This three-dimensional wiring approach reduces the horizontal footprint and total transmission path length simultaneously, improving access performance without increasing the overall chip area.
Solution Approach 2:
The patent employs a nested structure where multiple conductive wire layers are stacked vertically, with each layer containing transmission paths for specific word line groups. Via holes nest through the layers to provide vertical interconnections. This nested multi-layer architecture packs more transmission paths into a smaller horizontal area, reducing both path length and layout area while maintaining or improving access performance.
Data Source
AI summary
A three dimension memory device including a plurality of word lines, a plurality of first switches, a plurality of second switches and N conductive wire layers is provided, where N is a positive integer larger than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. A first word line group is connected to a first conductive wire layer through a second conductive wire layer. An ith word line group is connected to the first conductive wire layer through an (i+1)th to the second conductive wire layer in sequence.