3D Memory Word-Line Layout for Smaller Driver Footprints
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Solution Overview
Problem
Three-dimensional memory devices face challenges in integrating driving devices due to increased storage capacity, which requires a significant amount of space and makes it difficult to scale down word line drivers effectively.
Innovation Solution
The memory device employs a stacking structure with alternating word lines and isolation layers, featuring staircase and connection portions that allow word lines to extend continuously across sub-arrays, reducing the need for extensive driving current and enabling smaller word line drivers, while using ferroelectric switching layers and conductive pillars to form transistors that store data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory is used to increase storage capacity, then storage density is improved, but the area required for driving devices increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking structure, where memory cells are arranged vertically across multiple layers. This dimensional change allows storage capacity to increase without proportionally increasing the footprint area, as cells are stacked in the vertical dimension rather than spread out horizontally.
Solution Approach 2:
The patent merges multiple sub-arrays into a single three-dimensional stacking structure, sharing common word lines and control circuits across multiple layers. This consolidation reduces the total area required for driving devices by eliminating redundant components that would be needed in separate two-dimensional arrays.
2Quantity of substance
If storage capacity is increased through three-dimensional stacking, then more data can be stored, but integration of driving devices becomes more difficult
Solution Approach 1:
The patent implements shared word lines that serve multiple sub-arrays simultaneously across different layers. This multi-functional approach allows a single word line to control memory cells in multiple sub-arrays, reducing the total number of driving devices needed and simplifying integration compared to having dedicated word lines for each sub-array.
Solution Approach 2:
The patent divides the three-dimensional memory into multiple sub-arrays that can be independently addressed and controlled. This segmentation allows the memory system to manage large storage capacity by breaking it into smaller, more manageable units that share common control infrastructure, reducing overall integration complexity.
3Area of stationary object
If word line drivers are scaled down to reduce area, then footprint is reduced, but driving ability may be compromised
Solution Approach 1:
The patent combines multiple sub-arrays under shared word lines, which allows smaller, lower-power word line drivers to suffice. The drivers need only control a portion of the total memory capacity at any given time rather than the entire array, enabling area reduction while maintaining adequate driving ability through the merged architecture.
Data Source
AI summary
A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device include a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.