3D Memory Word Line Structure for GIDL and Leakage Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing gate-induced drain leakage (GIDL) and leakage current, which affect memory cell density and power consumption, especially in three-dimensional memory cell structures.
Innovation Solution
The implementation of a triple work function electrode structure for the word line, combined with a specific recess process for forming horizontal conductive lines, helps in reducing GIDL and leakage current by creating a low electric field and high threshold voltage, thereby enhancing memory cell integration density and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional single work function electrode structure is used for the word line, then the device structure is simple, but gate-induced drain leakage (GIDL) and leakage current increase
Solution Approach 1:
The word line is divided into multiple electrode segments (first work function electrode, second work function electrode, and third work function electrode) with different work functions. This segmentation allows each electrode to serve a specific function: the first and third electrodes with lower work functions reduce GIDL at their respective interfaces, while the second electrode with higher work function provides threshold voltage control, thereby reducing overall leakage current without excessive complexity
Solution Approach 2:
Different work function electrodes are applied at different locations along the word line structure. The first work function electrode is positioned at the interface with the bit line, the third work function electrode is positioned at the interface with the data storage element, and the second work function electrode is positioned in the middle. This local quality approach targets GIDL reduction specifically at the interfaces where it occurs most, rather than uniformly across the entire word line
2Quantity of substance
If memory cell density is increased through three-dimensional stacking, then capacity improves, but leakage current and GIDL increase
Solution Approach 1:
The patent implements three-dimensional memory cell stacking with multiple memory cells arranged vertically, increasing storage capacity. Simultaneously, the triple work function electrode structure is applied to each memory cell in the stack, with each electrode performing its specific function to suppress GIDL and leakage current. This allows high-density 3D integration while maintaining low leakage through the distributed electrode structure across multiple dimensional layers
3Loss of energy
If power consumption is reduced, then energy efficiency improves, but memory cell performance may deteriorate
Solution Approach 1:
The patent changes the work function parameter of the electrode materials to optimize both power consumption and performance. By selecting materials with specific work functions for each electrode position, the structure achieves low GIDL and leakage current (reducing power consumption) while maintaining adequate threshold voltage control (preserving memory cell performance). The specific work function values are tuned to balance these competing requirements
Data Source
AI summary
A semiconductor device including highly integrated memory cells and a method for fabricating the same in which the method includes: forming a semiconductor layer pattern over a lower structure; forming a gate dielectric layer covering the semiconductor layer pattern; forming a conductive layer surrounding the semiconductor layer pattern over the gate dielectric layer; forming a pair of horizontal conductive layer patterns respectively disposed over an upper surface and a lower surface of the semiconductor layer pattern by selectively etching the conductive layer; forming a horizontal layer having a side portion between the pair of horizontal conductive layer patterns by selectively recessing the semiconductor layer pattern; and forming a pair of horizontal conductive lines respectively disposed over an upper surface and a lower surface of the horizontal layer by recessing the pair of horizontal conductive layer patterns.