3D Double-Density Memory Array Word Line Sharing

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Solution Overview

Problem

Conventional double-density 3D memory arrays face issues with high word line resistance and complex manufacturing due to numerous word line connections, leading to low process yields and unstable patterns.

Innovation Solution

A double-density 3D memory array design where word lines are connected across both channels of a string, reducing the number of word lines and decoders, and employing specific etching processes to stabilize patterns, resulting in lower resistance and improved manufacturing yields.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional double-density 3D arrays use separate word lines for each vertical string, then each string can be independently addressed, but word line resistance increases and the number of decoders increases

Engineering Contradiction:
Improveindependent string addressingVSAvoidword line resistance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent merges the word line connections by having a single word line serve both vertical strings in a double-density configuration. This is achieved by connecting the word line to control gates on both strings, allowing the same word line signal to address memory cells in both strings simultaneously, thereby reducing the total number of word lines and decoders while maintaining addressing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The word line is designed to perform multiple functions by addressing memory cells in both vertical strings. The same word line structure and signal are universally applied to control gates on both strings, making the word line system multi-functional rather than requiring separate dedicated word lines for each string.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If conventional arrays have many word line connections, then more memory cells can be addressed, but manufacturing process yields decrease and word line patterns become unstable

Engineering Contradiction:
Improvememory cell addressing capacityVSAvoidprocess yields
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent combines multiple word line connections into a single shared word line structure. Instead of forming separate word line patterns for each vertical string, the manufacturing process forms one word line pattern that connects to control gates on both strings, simplifying the lithography and etching processes while improving manufacturing yields.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of operation

If separate word lines are used for each vertical string, then addressing is simplified, but the number of decoders and overall device complexity increases

Engineering Contradiction:
Improveaddressing simplicityVSAvoidnumber of decoders
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the decoder requirements by using a single decoder output to drive the shared word line that addresses both vertical strings. This eliminates the need for separate decoders for each string, reducing the overall number of decoders and associated complexity while maintaining the ability to independently address strings through selective activation.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20210296360A1Three dimensional double-density memory array
Publication Date: 2021.09.23 NEO SEMICON INC
  • US20210296360A1 patent drawing
  • US20210296360A1 patent drawing
  • US20210296360A1 patent drawing

AI summary

A three dimensional double-density memory array is disclosed. In an embodiment, a three-dimensional (3D) double density array comprises a string of memory devices that are configured so that a first portion of the memory devices form a first channel and a second portion of the memory devices form a second channel. The array also comprises a plurality of word lines coupled to the string of memory devices. Each word line is coupled to a memory device that forms the first channel and a memory device that forms the second channel. The array also comprises at least one drain select gate that couples the first and second channels to a bit line.