3D Stacked Memory Cell Structure for Lower Word-Line Coupling
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Solution Overview
Problem
The challenge in increasing integration density of semiconductor devices is limited by the expensive and complex process equipment required for fine pattern formation in two-dimensional devices, necessitating the development of three-dimensional semiconductor memory devices with vertically arranged memory cells.
Innovation Solution
A semiconductor memory device design featuring vertically stacked channel patterns, word lines, data storage patterns, bit lines, and source lines, with ferroelectric field effect transistors and specific insulating and conductive materials, allowing for high integration density and nonvolatile memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then the fabrication process is simpler, but integration density is limited due to area constraints and expensive fine pattern forming equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple channel patterns (first channel pattern and second channel pattern) are stacked vertically above each other, with word lines extending horizontally between them. This vertical stacking enables higher integration density without requiring finer lateral patterning, thus avoiding the need for expensive fine pattern forming equipment while achieving increased capacity.
2Quantity of substance
If three-dimensional vertically stacked memory cells are used, then integration density increases, but device complexity increases due to multiple stacked components
Solution Approach 1:
The memory device is segmented into distinct functional layers: channel patterns, word lines, data storage patterns, bit lines, and source lines. Each segment performs a specific function, and their vertical stacking creates a modular structure that achieves high integration density while maintaining manageable complexity through functional separation.
Solution Approach 2:
The word lines serve multiple functions: they extend between both the first and second channel patterns, enabling control of multiple vertically stacked memory cells simultaneously. This multi-functionality reduces the number of separate components needed, thereby increasing integration density without proportionally increasing device complexity.
3Quantity of substance
If vertically stacked channel patterns with word lines are used, then integration density increases, but coupling noise between word lines may increase
Solution Approach 1:
Interlayer insulating patterns are positioned between vertically adjacent word lines to act as electrical insulators. These intermediary layers prevent direct electrical coupling between word lines, thereby reducing coupling noise while allowing the word lines to be closely spaced for high integration density.
Solution Approach 2:
The insulating properties are locally applied at specific interfaces between word lines using interlayer insulating patterns. This localized insulation strategy targets the specific problem of coupling noise between adjacent word lines without affecting other regions of the device, enabling high integration density while controlling noise in critical areas.
Data Source
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AI summary
A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.