3D Memory Cell Layout for Higher Word Line Density
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Solution Overview
Problem
Existing manufacturing methods for memory result in low arrangement density of word lines, bit lines, and active layers, leading to large memory sizes due to the conventional buried word line structure and bit line connection method.
Innovation Solution
The method involves forming word lines on bit lines and an active layer between them, with a thicker first dielectric layer acting as an isolation structure and a thinner second dielectric layer as a gate dielectric, allowing for closer arrangement and higher density of capacitors, thereby reducing memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional buried word line structure is used, then manufacturing process is simple, but arrangement density of word lines, bit lines, and active layers is low
Solution Approach 1:
The patent transitions from a conventional planar buried word line structure to a three-dimensional structure where word lines are formed on top of bit lines. This vertical stacking arrangement increases the arrangement density of word lines, bit lines, and active layers by utilizing the vertical dimension, thereby solving the contradiction between manufacturing simplicity and arrangement density.
Solution Approach 2:
The patent implements a nested structure where active layers are positioned between adjacent word lines, and bit lines are integrated into the same vertical stack. This nesting arrangement maximizes the utilization of space, allowing multiple functional elements to coexist in a compact volume, thus improving arrangement density without proportionally increasing structural complexity.
2Area of stationary object
If conventional bit line connection method is used, then manufacturing process is simple, but memory size is large
Solution Approach 1:
The patent merges the bit line and word line structures into a unified three-dimensional architecture where bit lines extend along a first direction and word lines extend along a second direction, with active layers positioned between the word lines. This integration reduces the overall memory footprint by eliminating separate connection regions and optimizing the spatial arrangement of conductive elements.
Solution Approach 2:
The patent reduces memory size by transitioning to a vertical stacking configuration where bit lines and word lines are arranged in three dimensions rather than extending horizontally. This dimensional change allows for more compact placement of bit lines, word lines, and active layers, thereby decreasing the overall memory footprint while maintaining electrical connectivity.
Data Source
AI summary
A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.