3D Memory Row Layout With Nested Word Lines for Higher DRAM Density
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Solution Overview
Problem
The integration level of semiconductor structures, particularly in Dynamic Random Access Memory (DRAM), needs to be improved to expand their application fields.
Innovation Solution
A three-dimensional semiconductor structure is designed with memory rows and cells arranged in a specific pattern, where word line structures extend into gaps between adjacent rows, utilizing substrate space more efficiently, and incorporating features like step-shaped ends and shared bit lines to enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in horizontal structures to increase storage capacity, then storage capacity is improved, but integration level remains limited
Solution Approach 1:
The patent transitions from traditional two-dimensional horizontal memory cell arrangement to a three-dimensional structure where word line structures extend vertically into gaps between adjacent memory rows. This dimensional change allows memory cells to be stacked and interconnected in multiple layers, significantly improving integration level while maintaining storage capacity expansion
Solution Approach 2:
The word line structures are designed to extend into the gaps between adjacent memory rows, creating a nested configuration where word lines are positioned within the inter-row spaces. This nesting approach maximizes space utilization and achieves higher integration density without increasing the footprint area
2Device complexity
If word line structures extend into gaps between memory rows, then integration level is improved, but fabrication complexity increases
Solution Approach 1:
The memory structure is divided into discrete memory rows with defined gaps, and word line structures are segmented to extend into specific gap regions. This segmentation allows for modular fabrication processes where each memory row and word line segment can be formed and positioned systematically, reducing overall fabrication complexity despite the three-dimensional configuration
Data Source
AI summary
Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.