3D Non-Volatile Memory Layout for Compact Word-Line Routing
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Solution Overview
Problem
As the number of word lines stacked on a substrate increases in three-dimensional memory devices, the number of pass transistors connected to these lines also increases, leading to a rise in the complexity and length of connection wirings, which can reduce the reliability of memory devices due to coupling defects.
Innovation Solution
A non-volatile memory device design with a first semiconductor layer containing memory cells and a second semiconductor layer with pass transistors, where word line pads are arranged in a stair shape and connected by word line contacts, allowing for efficient overlap and alignment of pass transistors, reducing the chip size and maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on a substrate increases, then the storage capacity of the memory device is improved, but the number of pass transistors and connection wirings increases, leading to increased device complexity and reduced reliability
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture where word lines are arranged vertically across multiple layers. Word line pads are positioned at different heights in the vertical direction, and word line contacts connect these pads through vertical pathways. This dimensional change allows multiple word lines to be interconnected in space without proportionally increasing the footprint area, thereby managing complexity while maintaining high storage capacity.
Solution Approach 2:
The patent implements a nested structure where word line pads at different vertical levels are interconnected through word line contacts that penetrate through intermediate layers. Each word line pad and contact pair is embedded within the three-dimensional stack, with lower-level pads and contacts serving as foundations for upper-level structures. This nesting approach consolidates multiple connections within a compact vertical volume, reducing overall device complexity.
2Quantity of substance
If the number of pass transistors connected to word lines increases, then the storage capacity is improved, but the length and complexity of connection wirings increase, reducing reliability due to coupling defects
Solution Approach 1:
The patent utilizes vertical stacking to reduce the horizontal traversal distance of connection wirings. Word line contacts extend vertically to connect pads at different heights, creating direct pathways that minimize wiring length. This three-dimensional connection approach reduces the total wiring length compared to planar expansions, thereby reducing coupling defects and improving reliability while maintaining increased storage capacity through additional pass transistors.
Solution Approach 2:
The patent divides the connection architecture into discrete modular units: individual word line pads at specific vertical positions, separate word line contacts for each pad, and distinct pass transistor regions. This segmentation allows each connection element to be independently optimized and positioned, reducing interdependencies and potential coupling defects between wirings while accommodating a larger number of pass transistors for enhanced storage capacity.
3Area of stationary object
If word line pads are arranged in a stair shape in the vertical direction, then the overlap area with pass transistors is optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs an asymmetric stair-shaped arrangement of word line pads where each successive pad level is offset horizontally relative to the previous level. This asymmetric positioning creates optimized overlap regions with pass transistors located in intermediate areas, maximizing space utilization and reducing the overall chip footprint. The asymmetric design allows compact integration while providing clear spatial differentiation between pads at various heights.
Solution Approach 2:
The patent applies different spatial characteristics to different regions: word line pads at higher levels are positioned to overlap with pass transistor regions, while lower-level pads have different positioning requirements. Each pad's position is locally optimized based on its vertical level and the location of associated pass transistors. This local quality approach enables efficient space utilization through the stair configuration while maintaining manufacturability by providing clear positional guidance for each pad.
Data Source
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AI summary
A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes memory cells electrically connected to bit lines each extending in a first direction (Y) and word lines each extending in a second direction (X) and stacked in a vertical direction (Z), word line pads (WLP) which respectively correspond to the word lines and are arranged in a stair shape, and word line contacts (WLC) respectively electrically connected to the word line pads. The second semiconductor layer includes pass transistors (PTR) respectively electrically connected to the word line contacts to respectively overlap the word line pads in the vertical direction. Each of the word line pads has a first width (Y1, Y2) in the first direction and a second width (X1, X2) in the second direction. Each of the pass transistors has a first pitch (P1y, P2y) in the first direction and a second pitch in the second direction (P1x, P2x).