3D Memory Word Line Layout for Driver Integration and Scaling
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Solution Overview
Problem
Two-dimensional non-volatile memory designs limit storage capacity, and integrating driving devices becomes challenging as storage capacity increases in three-dimensional memory structures.
Innovation Solution
A three-dimensional memory device with word lines extending through sub-arrays, featuring a stacking structure of alternately stacked isolation layers and word lines, switching layers, and channel layers, allowing for vertical cell stacking and efficient integration of driving devices through innovative transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cells are stacked vertically in three-dimensional memory to increase storage capacity, then storage density is improved, but the amount of driving devices required increases making integration more difficult
Solution Approach 1:
The memory array is divided into multiple sub-arrays, with each sub-array having its own dedicated word line drivers. This segmentation allows the driving devices to be distributed across different locations rather than concentrated in one area, making integration more manageable while supporting the increased storage capacity of the 3D vertical stack
Solution Approach 2:
Word line drivers are positioned in the third dimension (below the memory stack in the vertical direction) rather than only in the planar direction. This 3D placement strategy enables efficient use of available space and reduces the footprint area required for driving devices, addressing the integration difficulty while maintaining high storage density
2Area of stationary object
If word line drivers are placed below the memory array to reduce footprint area, then area utilization is improved, but wiring complexity increases
Solution Approach 1:
The memory array is segmented into multiple sub-arrays, each served by dedicated word line drivers positioned below their respective sub-arrays. This segmentation reduces the wiring distance and complexity compared to having all drivers located far from the memory stack, as each driver only needs to connect to its local sub-array
Solution Approach 2:
Connection structures (such as via holes and conductive layers) serve as intermediaries to efficiently route word line signals from the drivers below the memory array to the corresponding word lines in the vertical stack. These intermediary connection structures simplify the overall wiring complexity by providing direct, localized pathways rather than requiring long-distance routing
Data Source
AI summary
A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.