3D Memory Wordline Sharing Reduces RC Delay
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Solution Overview
Problem
Conventional two-dimensional semiconductor memories face issues with increased power consumption and performance degradation due to longer wordline lengths, which affect resistance and capacitance.
Innovation Solution
The implementation of three-dimensional semiconductor memories with wordline sharing across vertically stacked layers reduces wordline lengths, thereby decreasing resistance and capacitance, and improves area efficiency, power, and speed performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wordline length is increased to accommodate wider memory arrays in two-dimensional layouts, then memory capacity is improved, but power consumption increases and performance degrades
Solution Approach 1:
The patent transitions from a two-dimensional memory layout to a three-dimensional stacked architecture where multiple memory layers are vertically stacked. This dimensional change allows wordlines to be shared across layers, significantly reducing the effective wordline length in each individual layer while maintaining the overall memory capacity through vertical stacking of multiple layers.
2Quantity of substance
If wordline length is increased in two-dimensional memories, then memory capacity is improved, but performance degrades due to increased resistance and capacitance
Solution Approach 1:
By implementing vertical stacking of multiple memory layers, the patent reduces the horizontal wordline length in each layer. This dimensional reorganization decreases the total resistance and capacitance along wordlines, thereby improving signal integrity and memory access speed while maintaining high capacity through the stacked architecture.
Solution Approach 2:
The patent implements wordline sharing where a single wordline serves multiple memory cells across different vertical layers. This multi-functionality allows one wordline to control access to memory cells in multiple layers simultaneously, reducing the overall wordline length required in each individual layer and improving performance characteristics.
3Ease of manufacture
If two-dimensional memory layout is used, then manufacturing simplicity is maintained, but area efficiency and performance are limited
Solution Approach 1:
The patent extends the memory architecture from two to three dimensions by stacking multiple memory layers vertically. This approach significantly improves area efficiency by utilizing the vertical dimension, allowing much higher storage capacity within a smaller footprint while maintaining compatibility with existing semiconductor manufacturing processes through standardized stacking techniques.
Data Source
AI summary
A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.