3D Semiconductor Memory Cell Structure With Vertical Word Line Support
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Solution Overview
Problem
The integration degree of two-dimensional semiconductor memory devices is limited due to the high cost and complexity of miniaturization techniques required for pattern formation, necessitating the development of three-dimensional memory cells to enhance storage density.
Innovation Solution
A semiconductor memory device with a peripheral circuit, alternating stacks of dielectric and semiconductor layers, and vertically oriented word lines, along with contact plugs and supporters, is fabricated to create a highly integrated three-dimensional memory cell array, allowing for increased storage density without the need for expensive ultra-fine pattern forming equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern forming techniques to increase integration degree, then storage density is improved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking architecture. Multiple memory cell layers are stacked vertically with alternating conductive and insulating layers, enabling storage density improvement without requiring further miniaturization of individual cell patterns. This dimensional transition resolves the contradiction by achieving higher integration through vertical stacking rather than horizontal pattern scaling.
2Manufacturing precision
If ultra-fine pattern forming equipment is used to miniaturize patterns, then integration degree is improved, but manufacturing cost increases
Solution Approach 1:
The invention employs vertical stacking of memory cell layers in the third dimension, allowing standard lithography equipment to form patterns at relaxed dimensions while achieving high integration through multiple stacked layers. This approach eliminates the need for expensive ultra-fine pattern forming equipment, resolving the contradiction between manufacturing precision and manufacturing cost.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing simplified pattern structures. This segmentation allows each layer to be formed using conventional lithography without requiring ultra-fine patterning, while the stacked configuration achieves high integration density, thereby reducing manufacturing cost.
3Quantity of substance
If three-dimensional memory cell structures are implemented, then storage density is improved, but device structural complexity increases
Solution Approach 1:
The patent implements a regular alternating stack of conductive layers and insulating layers in the vertical dimension, creating a modular three-dimensional structure. This systematic stacking pattern, while three-dimensional in nature, follows a predictable and repeatable architecture that simplifies fabrication processes and reduces structural complexity compared to irregular three-dimensional designs, thereby achieving high storage density without excessive complexity.
Data Source
AI summary
A semiconductor memory device includes: a peripheral circuit portion including an interconnection; first and second word line stacks that are spaced apart from each other over the peripheral circuit portion, the first and second word line stacks including word lines, respectively; an alternating stack of dielectric layers that are positioned over the peripheral circuit portion and disposed between the first and second word line stacks; a first contact plug penetrating the alternating stack to be coupled to the interconnection; a second contact plug coupled to the word lines of the first and second word line stacks; a first line-shape supporter between the first word line stack and the alternating stack, and extending vertically from the peripheral circuit portion; and a second line-shape supporter between the second word line stack and the alternating stack, and extending vertically from the peripheral circuit portion.