3D Memory Word Line Contacts With Self-Aligned Via Structures
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in manufacturing self-aligned word line contact via structures, which are crucial for efficient memory storage and access, due to complexities in forming stepped surfaces and dielectric materials that align with electrically conductive layers.
Innovation Solution
The solution involves forming an alternating stack of insulating and sacrificial material layers, creating stepped surfaces, and using isotropic etch processes to form contact cavities and finned dielectric pillar structures, followed by replacing sacrificial layers with conductive layers and forming layer contact via structures that align with both conductive and dielectric pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form contact via structures in three-dimensional memory devices, then manufacturing process simplicity is maintained, but manufacturing precision and alignment of contact via structures with electrically conductive layers deteriorates
Solution Approach 1:
The patent applies preliminary action by forming sacrificial material layers and stepped surfaces before forming the contact openings. The sacrificial layers are deposited and patterned in advance to define the precise locations where contact vias will later be formed, ensuring self-alignment with the electrically conductive layers without requiring complex alignment steps during via formation.
Solution Approach 2:
The patent uses sacrificial material layers as intermediary structures that facilitate the formation of self-aligned contact vias. These sacrificial layers act as temporary mediators that define the via locations and are removed after the vias are formed, leaving precisely aligned contact openings without requiring complex direct alignment processes.
2Reliability
If self-aligned contact via structures are formed using complex stepped surfaces and dielectric materials, then contact alignment and memory device performance improve, but manufacturing process complexity increases
Solution Approach 1:
The patent implements self-service through self-aligned contact via formation where the contact openings automatically align with the electrically conductive layers. The process uses the existing layer structure itself to define the via locations, eliminating the need for separate alignment operations and reducing manufacturing complexity while improving reliability.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: forming sacrificial layers, creating contact openings through the sacrificial layers, and removing the sacrificial materials. This segmentation allows each stage to be optimized independently, making the overall complex process more manageable and easier to manufacture.
3Manufacturing precision
If conventional contact via formation methods are used, then manufacturing process simplicity is maintained, but contact alignment precision and memory access efficiency deteriorate
Solution Approach 1:
The sacrificial material layers serve as intermediary structures that enable precise contact alignment. By using these temporary mediators to define via locations, the process achieves high alignment precision that directly improves memory access efficiency, as properly aligned contacts ensure reliable electrical connections to the memory elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of self-aligned contact via structures that enhance memory device performance by improving contact alignment and efficiency, leading to better memory access and storage capabilities.
Implementation Method 1
laterally expanding the contact cavities by performing an isotropic etch process that laterally recesses proximal portions of the insulating layers around each of the contact cavities selective to the electrically conductive layers
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.