3D Memory Electrode Stack With Work-Function-Split Resistance Control
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Solution Overview
Problem
Current 3D memory devices face challenges in increasing integration density and reducing source/drain resistance due to the vertical stacking of memory cells, which leads to increased total resistance and poor performance.
Innovation Solution
A memory device with a vertical structure featuring alternately stacked electrode layers and gate dielectric layers, where the effective work functions of the electrode and gate dielectric combinations differ, allowing for controlled source/drain regions and reduced resistance by using portions of the active region as both source/drain and channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacking of memory cells is implemented to increase integration density, then the number of stacked memory cells increases, but the total source/drain resistance increases
Solution Approach 1:
The gate structure is segmented into multiple electrode layers (first electrode layer, second electrode layer, third electrode layer) with different work functions positioned at different vertical levels. This segmentation allows independent control of source/drain regions at different heights, enabling reduced resistance in lower regions while maintaining memory functionality in upper regions.
Solution Approach 2:
Different portions of the active region are assigned different functions based on their vertical position. The lower portion serves as source/drain region with reduced resistance through control by the first electrode layer, while the upper portion serves as channel region controlled by the second and third electrode layers. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Device complexity
If the same electrode layer controls both source/drain and channel regions, then device structure is simplified, but resistance control precision deteriorates
Solution Approach 1:
The gate structure is divided into multiple electrode layers with different work functions, where each layer independently controls specific regions. The first electrode layer controls source/drain regions, while the second and third electrode layers control channel regions. This segmentation enables precise resistance control without excessive structural complexity.
Solution Approach 2:
The work function parameter is varied across different electrode layers to achieve different control characteristics. The first electrode layer has a work function optimized for source/drain control, while the second and third electrode layers have work functions optimized for channel control, enabling precise resistance management.
Data Source
AI summary
A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure. A first effective work function of a combination of the first electrode layer and the first gate dielectric layer is different from a second effective work function of a combination of the second electrode layer and the second gate dielectric layer.