3D Memory Wrap-Around Word Lines for Capacitive Coupling
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving enhanced capacitive coupling with discrete charge storage regions, which limits their performance in terms of program and erase speed and capacity.
Innovation Solution
The development of a three-dimensional memory device with wrap-around word lines, featuring a vertical stack of discrete charge storage elements surrounded by inner clam-shaped metallic liners and outer clam-shaped metallic liners with embedded metallic fill material, enhancing capacitive coupling and manufacturing methods that include forming alternating stacks of insulating and sacrificial layers, replacing semiconductor liners with metallic liners, and depositing charge storage elements and tunneling dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional memory devices are used, then manufacturing is simpler, but capacitive coupling with discrete charge storage regions is insufficient
Solution Approach 1:
The patent implements nested metallic liner structures where inner clam-shaped metallic liners are positioned within outer clam-shaped metallic liners, both surrounding the discrete charge storage regions. This nested configuration maximizes the surface area for capacitive coupling while maintaining a compact vertical structure, directly addressing the insufficient capacitive coupling in conventional devices.
Solution Approach 2:
The patent transitions from planar or simple vertical structures to wrap-around word lines that extend laterally and vertically in three dimensions. The metallic liners and charge storage elements are arranged in multiple vertical levels, creating a three-dimensional capacitive coupling architecture that significantly enhances coupling efficiency.
2Speed
If program and erase speed are increased, then memory performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the charge storage function into discrete charge storage regions arranged in multiple vertical levels, with each level having its own metallic liner structure. This segmentation allows for optimized capacitive coupling at each level, enabling faster program and erase operations while maintaining manufacturability through modular fabrication processes.
Solution Approach 2:
The patent changes the material parameters by introducing metallic liners with high electrical conductivity and appropriate work functions, and adjusts the geometric parameters by optimizing the size, shape, and spacing of the discrete charge storage regions. These parameter optimizations enhance capacitive coupling strength, enabling faster charge transfer during program and erase operations.
3Quantity of substance
If memory capacity is increased, then device functionality improves, but manufacturing difficulty increases
Solution Approach 1:
The patent increases memory capacity by utilizing the vertical dimension with multiple levels of discrete charge storage regions stacked above each other. Each level can store data independently, effectively multiplying the storage capacity within the same lateral footprint. The wrap-around word lines and metallic liners extend vertically to accommodate this multi-level architecture.
Solution Approach 2:
The nested metallic liner structure allows multiple discrete charge storage regions to be efficiently packaged within a compact volume. The inner and outer liners create defined spatial zones for charge storage, enabling high-density vertical stacking while maintaining manufacturing feasibility through standardized deposition and etching processes.
Data Source
AI summary
A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.


