3D Memory Block Interconnect for Defect-Tolerant Yield Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing three-dimensional memory devices result in a low yield due to the discarding of memory chips with even partial defects, leading to inefficient use of resources.
Innovation Solution
A three-dimensional device is designed with stacked circuit chips and an interconnect portion that connects non-defective circuit blocks, allowing defective blocks to be disconnected from the power source and interconnect, thereby improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory chips are tested and discarded when any portion is defective, then product reliability is ensured, but manufacturing yield decreases
Solution Approach 1:
The memory chip is divided into multiple independently testable and connectable circuit blocks. Instead of treating the entire chip as a single unit, each circuit block can be individually assessed for functionality and selectively connected to the interconnect portion, allowing partial utilization of chips with defects in certain blocks.
Solution Approach 2:
Different regions or blocks of the memory chip are treated differently based on their test results. Non-defective blocks are connected to the interconnect portion while defective blocks are disconnected, creating local quality variations that maximize usable capacity from each chip.
2Productivity
If all circuit blocks on a memory chip are connected to the interconnect portion, then device functionality is maximized, but defective blocks cause reliability issues
Solution Approach 1:
Circuit blocks are tested before being connected to the interconnect portion. This preliminary testing allows identification of defective blocks, which are then excluded from connection, ensuring that only reliable blocks are integrated into the final device structure.
Solution Approach 2:
The presence of defective circuit blocks is converted into a benefit by using them as examples to refine the selective connection process. By identifying and excluding only the defective portions, the system transforms potential waste into an opportunity to optimize resource utilization and improve overall manufacturing efficiency.
3Manufacturing precision
If memory chips with partial defects are discarded, then product quality is maintained, but resource utilization efficiency decreases
Solution Approach 1:
Instead of discarding entire memory chips with partial defects, the system recovers usable value by selectively connecting only the non-defective circuit blocks to the interconnect portion. This approach maintains product quality standards while recovering and utilizing the functional portions of otherwise discarded resources.
Data Source
AI summary
When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.