3D Semiconductor Memory Zigzag Vertical Structures
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by expensive processing equipment, making it costly to increase pattern fineness and thus memory cell density, while three-dimensional semiconductor memory devices aim to overcome these limitations by developing new process technologies for lower manufacturing costs and maintaining reliability.
Innovation Solution
A three-dimensional semiconductor memory device with a stack structure on a substrate, featuring vertically arranged gate electrodes and bit lines, and a zigzag arrangement of vertical structures to enhance integration and reliability, utilizing a combination of gate electrodes, dielectric layers, and charge storage structures to optimize memory cell placement and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are highly integrated to increase pattern fineness, then memory cell density is improved, but manufacturing cost increases due to expensive processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking architecture. Multiple memory cell layers are stacked vertically with alternating patterns of first and second vertical structures, enabling significantly higher memory cell density without requiring proportionally more expensive processing equipment. This dimensional change allows the device to achieve high integration while controlling manufacturing costs.
2Ease of manufacture
If three-dimensional semiconductor memory devices are developed to increase integration, then manufacturing cost per bit is reduced, but device reliability may be compromised
Solution Approach 1:
The memory device is divided into multiple independent memory cell layers stacked vertically, with each layer containing memory cells formed between alternating first and second vertical structures. This segmentation allows for modular manufacturing and testing, where defects in one layer do not necessarily compromise the entire device. The segmented architecture enables controlled fabrication processes that maintain reliability while reducing cost per bit through higher density.
Solution Approach 2:
Different regions of the three-dimensional structure employ different vertical structure types (first and second vertical structures) with potentially different material compositions or structural characteristics optimized for their specific locations. This local quality approach allows tailored optimization of each region's properties to ensure reliable operation while maintaining overall cost efficiency through the three-dimensional architecture.
Data Source
AI summary
Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a stack structure that includes gate electrodes on a substrate. The three-dimensional semiconductor memory device includes a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure that penetrate the stack structure and are sequentially arranged in a zigzag shape along a first direction. Moreover, the three-dimensional semiconductor memory device includes a first bit line that extends in the first direction. The first bit line vertically overlaps the second vertical structure and the fourth vertical structure. Centers of the second and fourth vertical structures are spaced apart at the same distance from the first bit line. The first vertical structure is spaced apart at a first distance from the first bit line. The third vertical structure is spaced apart at a second distance from the first bit line.