3D-Stacked MEMS Semiconductor Architecture for Compact Ultrasound
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Solution Overview
Problem
Existing MEMS devices, such as capacitive micromachined ultrasonic transducers (CMUTs), are bulky and costly due to the need for central processing units, frames, and wired components, limiting their practical applications.
Innovation Solution
A semiconductor device with a three-dimensional vertical integration of MEMS components, including a MEMS component, analog circuit, high-performance chip, deep trench capacitor, and printed circuit board, which allows for compact and efficient operation without the need for bulky central processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MEMS devices use traditional centralized processing architecture with CPU, frames, and wired components, then processing capability is sufficient, but device size becomes bulky and cost increases
Solution Approach 1:
The patent merges the MEMS sensor array, analog front-end circuits, digital signal processing units, and memory into a single integrated chip. This consolidation eliminates the need for separate CPU, frames, and wired connections, directly reducing device volume while managing complexity through systematic integration of multiple functional blocks on one substrate
Solution Approach 2:
The patent transitions from a two-dimensional planar layout with centralized processing to a three-dimensional vertical integration architecture. Multiple processing layers are stacked above the MEMS sensor array, with signal paths routed vertically through through-silicon vias, enabling compact volume utilization while maintaining sufficient processing capability distributed across layers
2Volume of moving object
If MEMS devices integrate multiple components vertically, then device size reduces, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct fabrication stages: MEMS sensor array formation on a first substrate, separate analog circuit and digital processing circuit formation on second and third substrates, followed by sequential bonding. This segmentation allows each component to be optimized and manufactured independently before integration, managing overall manufacturing complexity through modular processing
Solution Approach 2:
The patent implements a nested structure where the MEMS sensor array resides on the bottom substrate, analog circuits are bonded on top of it, digital processing circuits are bonded on top of the analog circuits, and memory is integrated within the digital processing layer. This nested arrangement maximizes vertical space utilization, achieving compact device size while organizing complex manufacturing steps in a hierarchical sequence
Data Source
AI summary
A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.