3D MEMS Device Stacked Wafer Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current MEMS devices are constrained by 2D architectures, which limit the accessibility of sensor electrodes or actuators located above, beneath, or around the MEMS elements, making it difficult to transmit electrical signals while protecting the sensing elements, and existing packaging methods are costly and labor-intensive.
Innovation Solution
A MEMS device architecture that includes a top cap wafer, a central MEMS wafer, and a bottom cap wafer, with insulated conducting pathways extending from the bottom cap through the MEMS wafer to the top cap, allowing for the routing of electrical signals and enabling the placement of electrodes above, below, or around the MEMS structure, while being hermetically sealed to protect the sensing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional 2D planar architecture is used for MEMS devices, then manufacturing is simplified and cost is reduced, but accessibility to sensor electrodes or actuators located above, beneath, or around the MEMS elements is limited
Solution Approach 1:
The patent transitions from traditional 2D planar architecture to a 3D stacked wafer architecture. Multiple wafer layers (first wafer, second wafer, third wafer) are stacked vertically to create three-dimensional conducting pathways. This allows electrodes and conducting paths to be positioned above, beneath, and around MEMS elements, providing accessibility in multiple spatial dimensions while maintaining manufacturability through standard wafer fabrication processes.
2Reliability
If chip-level packaging with wire bonding is used, then electrical connections are established, but packaging complexity and cost increase significantly
Solution Approach 1:
The patent merges the electrical connection function directly into the device structure itself. Conducting pathways are integrated within the stacked wafer architecture, eliminating the need for separate wire bonding or chip-level packaging steps. The conducting paths are formed as part of the wafer fabrication process, combining the device structure and electrical interconnects into a single integrated unit.
Solution Approach 2:
The patent extracts the electrical connection function from the packaging process and integrates it directly into the device structure. By forming conducting pathways within the wafer stack during fabrication, the need for post-fabrication wire bonding and complex packaging is eliminated, simplifying the overall manufacturing process.
3Object-affected harmful factors
If hermetic sealing is implemented to protect MEMS sensing elements, then environmental protection is improved, but packaging cost and complexity increase
Solution Approach 1:
The patent merges the hermetic sealing function with the device structure itself. The stacked wafer configuration with bonded interfaces provides inherent hermetic sealing that protects the MEMS sensing elements while maintaining a simple overall structure. The sealing is achieved through the wafer bonding process rather than requiring separate packaging components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture allows for cost-effective and efficient electrical signal transmission and processing, reducing packaging complexity and cost by enabling wire-bond-free connections to integrated circuits, and supports 3D MEMS applications without the limitations of traditional 2D architectures.
Implementation Method 1
insulated conducting pathways extending from within the bottom cap wafer, through the MEMS wafer and through the top cap wafer, to the respective electrical contacts, for routing electrical signals from the bottom cap wafer to the electrical contacts on the top cap wafer
Implementation Method 2
The top cap wafer, the MEMS wafer and the bottom cap wafer are made of a silicon-based semiconductor. They are also preferably bonded with a conductive bond, such as by fusion bonding or with an electrically conductive bonding.
Data Source
AI summary
A MEMS device is provided. The device includes a MEMS wafer, a top cap wafer and a bottom cap wafer. The top and bottom cap wafers are respectively bonded to first and second sides of the MEMS wafer, the MEMS and cap wafers being electrically conductive. The outer side of the top cap wafer is provided with electrical contacts. The MEMS wafer, the top cap wafer and the bottom cap wafer define a cavity for housing a MEMS structure. The device includes insulated conducting pathways extending from within the bottom cap wafer, through the MEMS wafer and through the top cap wafer. The pathways are connected to the respective electrical contacts on the top cap wafer, for routing electrical signals from the bottom cap wafer to the electrical contacts on the top cap wafer. A method of manufacturing the MEMS device is also provided.


