3D Semiconductor Metal Layer Alignment for TSV-Free Vertical Connectivity
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing, particularly for custom products targeting smaller volume and less diverse markets, and the limitations of Through-Silicon-Via (TSV) technology in 3D Integrated Circuits (ICs) due to its large size, which restricts vertical connectivity and complicates the construction of complex 3D ICs with high yield and reliability.
Innovation Solution
The development of multilayer 3D IC devices using single crystal transistors with oxide-to-oxide bonding and metal-to-metal bonding techniques, allowing for reduced lithography steps and improved vertical connectivity through layer transfer methods such as SmartCut and ELTRAN, enabling the construction of complex 3D ICs with enhanced yield and reduced development costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used for 3D IC construction, then vertical connectivity is achieved, but the large size of TSVs restricts vertical connectivity and complicates construction
Solution Approach 1:
The patent segments the interconnect structure into multiple metal layers (first metal layer, second metal layer, third metal layer) with different functions and densities. The first metal layer provides high-density vertical interconnects, the second metal layer provides low-density vertical interconnects, and the third metal layer provides horizontal interconnects. This segmentation allows each layer to be optimized for its specific function, resolving the contradiction between achieving vertical connectivity and maintaining construction simplicity.
2Ease of manufacture
If mask set cost is reduced for custom products, then development cost decreases, but manufacturing precision and device density improvement are limited
Solution Approach 1:
The patent transitions from traditional 2D scaling to 3D stacking architecture, adding the vertical dimension to device construction. Multiple semiconductor layers are stacked vertically with interconnect structures connecting them, enabling significant device density improvement without requiring proportionally expensive mask sets for each additional dimension. This dimensional transition allows cost-effective scaling for custom products.
Data Source
AI summary
A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.