3D Metal-First Transistor Layout for High-Density Vertical Stacking
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors to single-digit nanometer nodes, leading to a desire for three-dimensional (3D) semiconductor circuits where transistors are stacked vertically.
Innovation Solution
A method for fabricating a semiconductor structure involves forming a stack of metal structures on a substrate, with each metal structure comprising a ring and pad contacts, and channel structures within the rings, enabling vertical stacking and electrical separation of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors are arranged in one plane (2D layout), then manufacturing processes are simpler and well-established, but transistor density per unit area is limited and scaling to single-digit nanometer nodes faces greater challenges
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangement to three-dimensional vertical stacking. Multiple transistor layers are stacked vertically with metal structures forming rings at different heights, enabling increased transistor density by utilizing the vertical dimension rather than only horizontal plane expansion.
Solution Approach 2:
The patent divides the transistor structure into multiple discrete layers stacked vertically. Each layer contains metal structures forming rings and channel structures, with electrical separation between layers. This segmentation allows independent fabrication and positioning of each layer while achieving high overall density.
2Manufacturing precision
If transistors are stacked vertically in 3D, then transistor density per unit area increases significantly, but fabrication processes become more complex and challenging
Solution Approach 1:
The patent forms metal structures and their associated rings and pad contacts in advance, before forming the channel structures. This preliminary action establishes the vertical framework and electrical connection paths early in the fabrication process, simplifying subsequent steps for creating and connecting transistor channels.
Solution Approach 2:
The patent introduces metal structures forming rings as intermediary elements between substrate and upper interconnections. These rings serve as both structural support and electrical connection points, mediating the complex vertical interconnections required for 3D stacked transistors and simplifying the overall fabrication architecture.
3Manufacturing precision
If metal structures form rings with pad contacts extending radially, then vertical alignment and electrical separation between stacked transistors are achieved, but fabrication steps require precise customization
Solution Approach 1:
The patent employs radial extension of pad contacts from vertically stacked metal rings to achieve precise horizontal positioning and electrical separation. This radial geometry in the horizontal plane, combined with vertical stacking, creates a three-dimensional coordinate system that enables precise alignment while maintaining electrical isolation between layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of higher density circuits with reduced costs, achieving compact and highly dense 3D semiconductor designs by customizing fabrication steps and enabling vertical interconnections.
Implementation Method 1
forming a sacrificial layer on the substrate can include epitaxially growing a sacrificial layer on the substrate
Implementation Method 2
forming a channel structure on the sacrificial layer can include epitaxially growing a channel structure on the sacrificial layer
Data Source
AI summary
Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.